Changes between Version 46 and Version 47 of InterconnexionNetworks

Timestamp:

Mar 19, 2013, 12:55:26 PM (12 years ago)

Author:

alain

Comment:

--

InterconnexionNetworks

@@ -5 +5 @@
 == 1. The interconnection networks ==
 
-The TSAR architecture uses the DSPIN network on chip infrastructure to define three independent networks, that are fully separated for dead-lock prevention :
+The TSAR architecture uses the DSPIN network on chip infrastructure to define three independent networks.
  
  * The '''Direct Network''' implements the 40 bits TSAR physical address space that is visible by the software. It  transports the direct READ, WRITE, LL, SC and CAS transactions from any VCI initiator (typically a L1 cache controller or another hardware coprocessor with a DMA capability) to any VCI target (typically a memory cache controller, or a memory mapped peripheral). All VCI packets are translated to DSPIN packets by specific VCI/DSPIN wrappers. There is actually two physically separated networks for command packets and response packets. Both networks have a two-level hierarchical structure with a local interconnect in each cluster (that can be implemented as a local crossbar, or as a local ring), and a global interconnect (implemented as a 2D mesh).
@@ -15 +15 @@
 
  * The '''External Network''' supports communications between the L2 caches and the ''tiles'' implementing the 3D L3 cache, in case of MISS or cache line replacement in the L2 caches. It has a 3D mesh topology and the DSPIN flit width is 64 bits. This external network addressing space is not visible by the software. 
-
- * A given hardware component can be connected to several networks. For example the L1 cache has one VCI initiator port to the direct network, and one DSPIN port to the coherence network. The L2 cache has one VCI target port on the direct network, one DSPIN port on the coherence network, and one DSPIN port to the external network.
 
 == 2.  VCI initiators & targets indexing on direct network ==