Changes between Version 50 and Version 51 of InterconnexionNetworks
- Timestamp:
- Mar 19, 2013, 1:11:00 PM (12 years ago)
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InterconnexionNetworks
v50 v51 50 50 Therefore, the total SRCID width cannot be larger than 14 bits. It can use less than 14 bits when the number of clusters is smaller than 1024. 51 51 52 == 3. VCI encoding of the various transaction typeson the direct network ==52 == 3. VCI encoding of the transaction on the direct network == 53 53 54 54 All Hardware components connected to the direct network respect the VCI/OCP communication interface. … … 111 111 * A VCI CAS response packet contains 1 flit. The RDATA field contains 0 (resp. 1) to indicate a CAS success (resp. failure). 112 112 113 == 4. DSPIN encoding of the various transaction typeson the direct network ==113 == 4. DSPIN packet encoding on the direct network == 114 114 115 115 The VCI command & response packets are translated (actually serialized) to DSPIN network format by the VCI/RING wrappers (in platform using the RING local interconnect) or by the VCI/DSPIN wrappers (in platforms using a XBAR local interconnect). These wrappers are located between the VCI initiator and target components and the DSPIN network. The DSPIN command packet width is 40 bits, and the DSPIN response packet width is 33 bits. The DSPIN interconnexion network uses only the following information to route the DSPIN packets to the proper destination: … … 171 171 || 1 || (32) || 172 172 173 == 5. DSPIN encoding of the coherence transactions173 == 5. DSPIN packet encoding on the coherence network 174 174 175 175 The coherence transactions are directly transmitted to the coherence network by the L1 caches and L2 caches in DSPIN format. The L2-to-L1 network uses 40 bits flits. The L1-to-L2 network uses 33 bits flits.
