Changes between Version 58 and Version 59 of InterconnexionNetworks


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Timestamp:
Apr 15, 2013, 11:49:20 AM (12 years ago)
Author:
alain
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  • InterconnexionNetworks

    v58 v59  
    77The TSAR architecture uses the DSPIN network on chip infrastructure to define three independent networks.
    88 
    9  * The '''Direct Network''' implements the 40 bits TSAR physical address space that is visible by the software. It  transports the direct READ, WRITE, LL, SC and CAS transactions from any VCI initiator (typically a L1 cache controller or another hardware coprocessor with a DMA capability) to any VCI target (typically a memory cache controller, or a memory mapped peripheral). All VCI packets are translated to DSPIN packets by specific VCI/DSPIN wrappers. There is actually two physically separated networks for command packets and response packets. Both networks have a two-level hierarchical structure with a local interconnect in each cluster (that can be implemented as a local crossbar, or as a local ring), and a global interconnect (implemented as a 2D mesh).
     9 * The '''Direct Network''' implements the 40 bits TSAR physical address space supporting software driven transactions. It  transports the direct READ, WRITE, LL, SC and CAS transactions from any VCI initiator (typically a L1 cache controller or another hardware coprocessor with a DMA capability) to any VCI target (typically a memory cache controller, or a memory mapped peripheral). All VCI packets are translated to DSPIN packets by specific VCI/DSPIN wrappers. There is two physically separated networks for command packets and response packets. Both networks have a two-level hierarchical structure with a local interconnect in each cluster (that can be implemented as a local crossbar, or as a local ring), and a global interconnect (implemented as a 2D mesh).
    1010
    1111 * The '''Coherence Network''' is used to transport the coherence packets implementing the DHCCP coherence protocol between L2 cache controllers and L1 cache controllers. This network is not visible by the software, and does not use wrappers, as the L1 and L2 cache controllers use directly the DSPIN packet format. Here again there is two physically separated networks to transport L2-to-L1 packets, and to transport L1-to-L2 packets. Both networks have a two-level hierarchical structure with a local interconnect in each cluster (that can be implemented as a local crossbar, or as a local ring), and a global interconnect (implemented as a 2D mesh).
    1212
    13  * The '''Direct Network''' and the '''coherence Network''' are physically separated in each cluster, but they are only logically separated for the global communications: Regarding the local interconnect, there is four physically separated local crossbars (or local rings) transporting the ''direct command'', ''direct response'', '' coherence L1-to-L2'', ''coherence L2-to-L1'' packets.  Regarding the global interconnect, the DSPIN infrastructure supporting two virtual channels, the ''direct command'' and the ''coherence L2-to-L1'' packets are multiplexed on the same 2D mesh (40 bits DSPIN flit width). Similarly, the ''direct response'' and ''coherence L1-to-L2'' packets are multiplexed on the same 2D mesh (33 bits DSPIN width).
    14 
    1513 * The '''External Network''' supports communications between the L2 caches and the ''tiles'' implementing the L3 cache, in case of MISS or cache line replacement in the L2 caches. It supports also the direct communication between the L3 cache and the external peripheral that have a DMA capability (Disk controllers, or network controllers). It has a 3D mesh topology and the DSPIN flit width is 64 bits. This external network addressing space is not visible by the software.
     14
     15Regarding implementation, the '''Direct Network''' and the '''coherence Network''' are physically separated in each cluster, but they are only logically separated for the global communications: For the local interconnect, there is four physically separated local crossbars (or local rings) transporting the ''direct command'', ''direct response'', '' coherence L1-to-L2'', ''coherence L2-to-L1'' packets.  For the global interconnect, we use the DSPIN virtual channels: the ''direct command'' and the ''coherence L2-to-L1'' packets are multiplexed on the same 2D mesh (40 bits DSPIN flit width). Similarly, the ''direct response'' and ''coherence L1-to-L2'' packets are multiplexed on the same 2D mesh (33 bits DSPIN flit width).
    1616
    1717== 2.  VCI initiators & targets indexing on direct network ==
    … …  
    2424
    2525The X_ID, Y_ID and L_ID are coded on NX, NY, NL bits respectively.
    26 The NX, NY and NL parameters are global for a given instance of the TSAR architecture.  NX & NY cannot be larger than 5 (no more than 1024 clusters), but can be smaller, if the number of clusters is smaller than 1024. NL is equal to 4 (no more than 16 target ports or 16 initiator ports per cluster).
     26The NX, NY and NL parameters are global for a given instance of the TSAR architecture.  NX & NY cannot be larger than 5 (no more than 1024 clusters), but can be smaller when the number of clusters is smaller than 1024. NL is equal to 4 (no more than 16 target ports or 16 initiator ports per cluster).
    2727
    2828In order to simplify the hardware implementation, the L_ID values defined for the direct network are
    … …  
    3737|| NX bits || NY bits || NLADR bits ||  40-NX-NY-NLADR ||
    3838
    39  * According to the NUMA characteristics of the TSAR architecture, there is no transcoding of the X & Y fields, that directly define the target cluster coordinates  (X_INDEX, Y_INDEX).
     39 * According to the NUMA characteristics of the TSAR architecture, there is no transcoding of the X & Y address fields, that directly define the target cluster coordinates  (X_ID, Y_ID).
    4040 * The network hardware decodes the LADR field to obtain the target L_ID, using a local routing table (implemented as a wired decoder in each local interconnect controller). The local routing tables and the number of bits NLADR to be decoded can depend on the cluster.
    4141
    … …  
    6666The TSAR architecture uses one single bit for the VCI RERROR field, even if the DSPIN infrastructure supports 2 bits for the error field.
    6767
    68 There are 8 transaction types on the direct network, that are encoded through the VCI fields '''CMD''' and '''PKTID'''. The PKTID MSB bit is ignored (reserved for future use).
     68There are 8 transaction types on the direct network, that are encoded through the VCI fields '''CMD''' and '''PKTID'''.
     69The PKTID MSB bit is ignored (reserved for future use).
    6970This redundant encoding help to use in the TSAR architecture existing hardware components that do not
    7071decode the PKTID field, and use only the CMD field.