Changes between Version 62 and Version 63 of InterconnexionNetworks


Ignore:
Timestamp:
Apr 15, 2013, 7:54:12 PM (12 years ago)
Author:
alain
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • InterconnexionNetworks

    v62 v63  
    2525The X_ID, Y_ID and L_ID are coded on NX, NY, NL bits respectively.
    2626The NX, NY and NL parameters are global for a given instance of the TSAR architecture.  NX & NY cannot be larger than 5 (no more than 1024 clusters), but can be smaller when the number of clusters is smaller than 1024. NL is equal to 4 (no more than 16 target ports or 16 initiator ports per cluster).
    27 
    28 In order to simplify the hardware implementation, the L_ID values defined for the direct network are
    29 also used on the coherence network, and the same value is used for an initiator port and for a target port: If the number of processors per cluster is NPROCS, the LI cache L_ID value is between 0 and (NPROCS-1).  The L2 cache L_ID is equal to NPROCS.
    3027
    3128=== 2.1 Target identification ===
    … …  
    565310 bits. Therefore, the local index L_ID cannot use more than 4 bits, even if NL is larger than 4.
    5754
    58 == 3.  VCI encoding of the transaction on the direct network ==
     55== 3. Component identification on the coherence network ==
     56
     57The only components connected on the coherence network are the processors (L1), and the memory
     58cache controler (L2). There is NPROCS L1 components and only one L2 component per cluster.
     59To route a coherence packet from a source component to a destination
     60component the DSPIN network uses the DEST field (left justified in the first flit of the packet).
     61
     62 * When the destination is a processor (L1), the DEST value is the processor SRCID (X_ID|Y_ID|L_ID), with L_ID between 0 and (NPROCS-1). 
     63 * When the destination is a memory cache (L2), the DEST value has the same structure (X_ID|Y_ID|L_ID), with L_ID = NPROCS.
     64
     65== 4.  VCI encoding of the transaction on the direct network ==
    5966
    6067All Hardware components connected to the direct network respect the VCI/OCP communication interface.
    … …  
    9097When a given initiator can send several simultaneous transactions of a given type (such as several simultaneous WRITE transactions), the VCI '''TRDID''' field is used to discriminate them. The '''TRDID''' field is 4 bits, supporting up to 16 simultaneous transactions for a given initiator.
    9198
    92 === 3.1 VCI READ transaction ===
     99=== 4.1 VCI READ transaction ===
    93100
    94101 * A VCI READ command packet contains one flit. In case of burst, all addresses must be within the same cache line. The VCI TRDID field is not used by L1 cache, but can be used by multi-channel DMA controllers to transmit the channel index.
    95102 * A VCI READ response packet returns up to 16 flits.
    96103
    97 === 3.2 VCI WRITE transaction ===
     104=== 4.2 VCI WRITE transaction ===
    98105
    99106 * A VCI WRITE command packet contains from 1 to 16 flits. In case of burst, all addresses must within the same cache line. The VCI TRDID field is used by the L1 cache to index its write buffer. It can be used by multi-channel DMA controllers to transmit the channel index.
    100107 * A VCI WRITE response packet contains one single flit.
    101108
    102 === 3.3 VCI LL (Linked Load) transaction ===
     109=== 4.3 VCI LL (Linked Load) transaction ===
    103110
    104111 * This request is only sent by a L1 cache and can only target a memory cache.
    … …  
    106113 * A VCI LL response packet contains 2 flits: The first flit contains in the RDATA field a signature returned by the memory cache for this LL reservation. The second flit contains in the RDATA field the data that has been read in the memory cache.
    107114
    108 === 3.4 VCI SC (Store Conditional) transaction ===
     115=== 4.4 VCI SC (Store Conditional) transaction ===
    109116
    110117 * This request is only sent by a L1 cache and can only target a memory cache.
    … …  
    118125 * A VCI CAS response packet contains 1 flit. The RDATA field contains 0 (resp. 1) to indicate a CAS success (resp. failure).
    119126
    120 == 4.  DSPIN packet encoding on the direct network ==
     127== 5.  DSPIN packet encoding on the direct network ==
    121128
    122129The VCI command & response packets are translated (actually serialized) to DSPIN network format by the VCI/RING wrappers (in platform using the RING local interconnect) or by the VCI/DSPIN wrappers (in platforms using a XBAR local interconnect). These wrappers are located between the VCI initiator and target components and the DSPIN network. The DSPIN command packet width is 40 bits, and the DSPIN response packet width is 33 bits. The DSPIN interconnexion network uses only the following information to route the DSPIN packets to the proper destination:
    … …  
    130137If the SRCID field uses less than 14 bits (NX < 5 or NY < 5), the SRCID field is left aligned, and the LSB bits of the DSPIN field are completed with "0".
    131138
    132 === 4.1 DSPIN Read Command packet format (40 bits) ===
     139=== 5.1 DSPIN Read Command packet format (40 bits) ===
    133140
    134141A single flit VCI Read Command packet (this includes LL packets) is translated to a 2 flits DSPIN Read Command packet :
    … …  
    141148|| 1 || (14)||(2)||(2)|| (8)|| (4) || (4) ||(4)||(1)||
    142149
    143 === 4.2 DSPIN write Command packet format (40 bits) ===
     150=== 5.2 DSPIN write Command packet format (40 bits) ===
    144151A N flits VCI Write Command packet (this includes SC packets) is translated to a N+2 flits DSPIN Write Command packet :
    145152
    … …  
    155162
    156163
    157 === 4.3 DSPIN single flit Response packet format (33 bits) ===
     164=== 5.3 DSPIN single flit Response packet format (33 bits) ===
    158165
    159166A single flit DSPIN Response packet is built for the following VCI response packets:
    … …  
    166173|| 1 || (14) || (2)  || (4)  || (4)  ||(7)|| 0||
    167174
    168 === 4.4 DSPIN multi-flit Response packet format (33 bits) ===
     175=== 5.4 DSPIN multi-flit Response packet format (33 bits) ===
    169176
    170177For all other VCI response packets (multi-flits VCI response packet, or non-zero RDATA value)
    … …  
    178185|| 1 ||                (32)                        ||
    179186
    180 == 5. DSPIN packet encoding on the coherence network
     187== 6. DSPIN packet encoding on the coherence network
    181188
    182189The coherence transactions are directly transmitted to the coherence network by the L1 caches and L2 caches in DSPIN format.
    … …  
    203210||MULTI-ACK   ||  0   ||  *   ||
    204211
    205 === 5.1 DSPIN MULTI-UPDATE packet format (L2-to-L1 : 40 bits) ===
     212=== 6.1 DSPIN MULTI-UPDATE packet format (L2-to-L1 : 40 bits) ===
    206213
    207214This DSPIN packet contains 2+N flits.
    … …  
    226233||1  ||(3)  ||(4) ||             (32)                  ||
    227234
    228 === 5.2 DSPIN MULTI-INVAL packet format (L2-to-L1 : 40 bits) ===
     235=== 6.2 DSPIN MULTI-INVAL packet format (L2-to-L1 : 40 bits) ===
    229236
    230237This DSPIN packet contains 2 flits.
    … …  
    242249||1  ||(1)|| (4)||               (34)                   ||
    243250 
    244 === 5.3 DSPIN BROADCAST packet format (L2-to-L1 : 40 bits) ===
     251=== 6.3 DSPIN BROADCAST packet format (L2-to-L1 : 40 bits) ===
    245252
    246253This DSPIN packet contains 2 flits.
    … …  
    256263|| 1 ||(5)||                     (34)                     ||
    257264
    258 === 5.4 DSPIN CLEANUP-ACK packet format (L2-to-L1 : 40 bits) ===
     265=== 6.4 DSPIN CLEANUP-ACK packet format (L2-to-L1 : 40 bits) ===
    259266
    260267This DSPIN packet contains one flit.
    … …  
    268275
    269276
    270 === 5.5 DSPIN CLEANUP packet format (L1-to-L2 : 33 bits)
     277=== 6.5 DSPIN CLEANUP packet format (L1-to-L2 : 33 bits)
    271278
    272279This DSPIN packet contains 2 flits.
    … …  
    285292||1  ||               (32)                              ||
    286293
    287 === 5.6 DSPIN MULTI-ACK packet format (L1-2-L2 : 33 bits) ===
     294=== 6.6 DSPIN MULTI-ACK packet format (L1-2-L2 : 33 bits) ===
    288295
    289296This DSPIN packet contains one flit.
    … …  
    296303|| 1 ||   (10) ||       (15)        || (4) ||(2) ||0 ||
    297304
    298 == 6.  External Network ==
     305== 7.  External Network ==
    299306
    300307TBD