Changes between Version 66 and Version 67 of InterconnexionNetworks
- Timestamp:
- Apr 22, 2013, 1:59:33 PM (12 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
InterconnexionNetworks
v66 v67 11 11 * The '''Coherence Network''' is used to transport the coherence packets implementing the DHCCP coherence protocol between L2 cache controllers and L1 cache controllers. This network is not visible by the software, and does not use wrappers, as the L1 and L2 cache controllers use directly the DSPIN packet format. Here again there is two physically separated networks to transport L2-to-L1 packets, and to transport L1-to-L2 packets. Both networks have a two-level hierarchical structure with a local interconnect in each cluster (that can be implemented as a local crossbar, or as a local ring), and a global interconnect (implemented as a 2D mesh). 12 12 13 * The '''External Network''' supports communications between the L2 caches and the ''tiles'' implementing the L3 cache, in case of MISS or cache line replacement in the L2 caches. It supports also the direct communication between the L3 cache and the external peripheral that have a DMA capability (Disk controllers, or network controllers). It has a 3D mesh topology and the DSPIN flit width is 64 bits. This external network addressing space is not visible by the software.13 * The '''External Network''' supports communications between the L2 caches and the ''tiles'' implementing the L3 cache, in case of MISS or cache line replacement in the L2 caches. It supports also the direct communication between the external peripheral that have a DMA capability (Disk controllers, or network controllers) and the L3 cache. It has a 3D mesh topology and the DSPIN flit width is 64 bits. This external network addressing space is not visible by the software. 14 14 15 15 Regarding implementation, the '''Direct Network''' and the '''coherence Network''' are physically separated in each cluster, but they are only logically separated for the global communications: For the local interconnect, there is four physically separated local crossbars (or local rings) transporting the ''direct command'', ''direct response'', '' coherence L1-to-L2'', ''coherence L2-to-L1'' packets. For the global interconnect, we use the DSPIN virtual channels: the ''direct command'' and the ''coherence L2-to-L1'' packets are multiplexed on the same 2D mesh (40 bits DSPIN flit width). Similarly, the ''direct response'' and ''coherence L1-to-L2'' packets are multiplexed on the same 2D mesh (33 bits DSPIN flit width). … … 303 303 || 1 || (10) || (15) || (4) ||(2) ||0 || 304 304 305 == 7. VCI initiators & targets on the external network == 305 == 7. Initiators & targets on the external network == 306 307 The L3 cache is implemented as a set of physical memory banks, with one single memory bank per cluster. 306 308 307 309 The only targets on the external network are the physical memory bank (one target per cluster). 308 The initiators are the memory cache (one initiator per cluster) and the I/O bridge (one extra initiator in the I/O cluster. 309 As for the direct network, each VCI port is identified by three indexes : 310 311 * '''X_ID''' is the cluster X-coordinate in the 2D mesh. 312 * '''Y_ID''' is the cluster Y-coordinate in the 2D mexh. 313 * '''L_ID''' is the local index inside the cluster. 314 315 X_ID, Y_ID and L_ID are coded on NX, NY, NL bits respectively. 316 The local index is only used to discriminate the initiators. It is not used by the targets. 317 318 || Initiator ||L_ID|| 319 || || || 320 || memory cache || 0 || 321 || I/O bridge || 1 || 322 323 Here is the VCI encoding on the external network 324 325 || VCI Field || width || 326 || || || 327 ||ADDRESS || 40 bits || 328 ||WDATA , RDATA || 64 bits || 329 ||PLEN || 7 bits || 330 ||SRCID, RSRCID || 14 bits || 331 ||TRDID, RTRDID || 4 bits || 332 ||PKTID, RPKTID || 0 bits || 333 ||RERROR || 1 bit || 334 335 The only supported transactions are READ and WRITE transactions. 336 Bursts are supported, but all addresses in a burst 337 Only should be in the same cache line (64 bytes). 338 We don't transport the VCI BE field on the external network, as the byte operations are not supported. 339 We don't transport the VCI PKTID field 340 341 == 8. DSPIN packet encoding on the direct network == 342 343 The VCI command & response packets are translated (actually serialized) to DSPIN format by the VCI/DSPIN wrappers. For both the DSPIN command packet and the response packet, the flit width is 65 bits. and the DSPIN response packet width is 33 bits. 344 The DSPIN interconnexion network uses only the following information to route the DSPIN packets to the proper destination: 310 The initiators are the memory cache (one initiator per cluster) and the I/O bridge (one extra initiator in the I/O cluster). 311 The I/O bridge is acting as a multiplexer for the various DMA commands sent by the external peripherals. 312 313 As for the direct network, each initiator is identified by three indexes X_ID (cluster X-coordinate), Y_ID (cluster Y-coordinate), 314 and L_ID (local index). The L_ID value 0 is reserved for the memory cache. L-ID values larger than 0 must be allocated to the various external peripherals. 315 316 * The only supported transactions are READ and WRITE burst transactions, 317 * All addresses must be aligned on 32 bits word boundary, 318 * All addresses in the same burst must be in the same cache line (64 bytes), 319 * Byte operations are not supported. 320 321 The external network is implemented as a 2D mesh, using DSPIN routers with a 65 bits flit width, 322 where the DATA field in a flit is 64 bits. The memory cache and I/O bridge components are directly 323 connected to the external network through DSPIN_65 interfaces. 324 325 The various fields in the DSPIN_65 command and response packets are defined below: 326 he following features are implemented in the VCI/DSPIN wrappers: 327 328 * ADDRESS: Only the 38 MSB bits of the physical 40 bits address are transported in a DSPIN command packet. 329 * WLEN: This argument define the number of 32 bits words in a burst (WLEN = (PLEN/4) - 1). 330 * SRCID: Initiator identifier (X_ID | Y_ID | L_ID) coded on 14 bits. 331 * TRDID: Transaction identifier for simultaneous transactions from a given initiator. 332 * CMD: Transaction type ( 00 == READ / 01 == WRITE / 1* == reserved ) 333 * ERROR: Transaction status ( 00 == Read Success / 01 == Read Error / 10 == Write Success / 11 == Write Error) 334 335 == 8. DSPIN_65 packet encoding on the external network == 336 337 The DSPIN_65 network uses only the following information to route the DSPIN packets to the proper destination: 345 338 * The EOP flag, defining the last flit of a DSPIN packet. 346 * The (NX+NY+NL) MSB bits of the first field are used to route the packet to the proper destination. 347 339 * The 14 MSB bits of the first field are used to route the DSPIN packet. 348 340 349 341 === 8.1 DSPIN Read Command packet format (65 bits) === … … 352 344 353 345 Flit 0 : 354 ||EOP||----------------ADDRESS--------------- -----||PLEN||CMD||SRCID||TRDID||355 || 1 || (38) || (7)||(1)|| (14)|| (4) ||346 ||EOP||----------------ADDRESS---------------||res||WLEN||CMD||SRCID||TRDID|| 347 || 1 || (38) ||(2)|| (4)||(2)|| (14)|| (4) || 356 348 357 349 === 8.2 DSPIN write Command packet format (65 bits) === … … 361 353 362 354 Flit 0 : 363 ||EOP||----------------ADDRESS--------------- -----||PLEN||CMD||SRCID||TRDID||364 || 0 || (38) || (7)||(1)|| (14)|| (4) ||355 ||EOP||----------------ADDRESS---------------||res||WLEN||CMD||SRCID||TRDID|| 356 || 1 || (38) ||(2)|| (4)||(2)|| (14)|| (4) || 365 357 366 358 Flit N : … … 373 365 374 366 Flit 0 : 375 ||EOP||RSRCID||------------ res --------------------------- ||RERROR||RTRDID||376 || 0 || (14) || (44) || (2) || (4)||367 ||EOP||RSRCID||------------ res -----------------------------||ERROR||TRDID|| 368 || 0 || (14) || (44) || (2) || (4) || 377 369 378 370 Flit N :
