Changes between Version 68 and Version 69 of InterconnexionNetworks
- Timestamp:
- Apr 22, 2013, 2:12:27 PM (12 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
InterconnexionNetworks
v68 v69 13 13 * The '''External Network''' supports communications between the L2 caches and the ''tiles'' implementing the L3 cache, in case of MISS or cache line replacement in the L2 caches. It supports also the direct communication between the external peripheral that have a DMA capability (Disk controllers, or network controllers) and the L3 cache. It has a 3D mesh topology and the DSPIN flit width is 64 bits. This external network addressing space is not visible by the software. 14 14 15 Regarding implementation, the '''Direct Network''' and the '''coherence Network''' are physically separated in each cluster, but they are only logically separated for the global communications: For the local interconnect, there is four physically separated local crossbars (or local rings) transporting the ''direct command'', ''direct response'', '' coherence L1-to-L2'', ''coherence L2-to-L1'' packets. For the global interconnect,we use the DSPIN virtual channels: the ''direct command'' and the ''coherence L2-to-L1'' packets are multiplexed on the same 2D mesh (40 bits DSPIN flit width). Similarly, the ''direct response'' and ''coherence L1-to-L2'' packets are multiplexed on the same 2D mesh (33 bits DSPIN flit width).15 Regarding implementation, the '''Direct Network''' and the '''coherence Network''' are physically separated for the local interconnect, as there is four physically separated local crossbars (or local rings) transporting the ''direct command'', ''direct response'', '' coherence L1-to-L2'', ''coherence L2-to-L1'' packets. But they are only logically separated for the global interconnect, as we use the DSPIN virtual channels: the ''direct command'' and the ''coherence L2-to-L1'' packets are multiplexed on the same 2D mesh (40 bits DSPIN flit width). Similarly, the ''direct response'' and ''coherence L1-to-L2'' packets are multiplexed on the same 2D mesh (33 bits DSPIN flit width). 16 16 17 17 == 2. VCI initiators & targets identifiers on direct network == … … 357 357 358 358 Flit N : 359 ||EOP||-------------------------------- WDATA-----------------------------------||360 || 1 || (64) ||359 ||EOP||---------------------------------WDATA-----------------------------------|| 360 || 1 || (64) || 361 361 362 362 === 8.3 DSPIN Read Response packet format (65 bits) === … … 369 369 370 370 Flit N : 371 ||EOP||------------------------------- RDATA------------------------------------||372 || 1 || (64)||371 ||EOP||--------------------------------RDATA------------------------------------|| 372 || 1 || (64) || 373 373 374 374 === 8.4 DSPIN Write Response packet format (65 bits) ===