Changes between Version 4 and Version 5 of Specification
- Timestamp:
- Jul 15, 2009, 9:58:49 AM (15 years ago)
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Specification
v4 v5 19 19 20 20 21 Each memory bank is actually implemented as a memory cache : A memory cache is not a classical level 2 cache. The physical address space is statically split into fixed size segments, and each memory cache is responsible for 21 Each memory bank is actually implemented as a memory cache : A memory cache is not a classical level 2 cache. The physical address space is statically split into fixed size segments, and each memory cache is responsible for one segment, defined by the physical address MSB bits. With this principle, it is possible to control the physical placement of the data by controlling the address values. 22 22 23 23 … … 25 25 == 3. Virtual memory support == 26 26 27 The TSAR architecture implements a paginated virtual memory. It defines a generic MMU (Memory Management Unit), physically implemented in the L1 cache controller. This generic MMU is independent on the 27 The TSAR architecture implements a paginated virtual memory. It defines a generic MMU (Memory Management Unit), physically implemented in the L1 cache controller. This generic MMU is independent on the processor core, and can be used with any 32 bits, single instruction issue RISC processor. To be independent from the processor core, the TLB MISS are handled by an hardwired FSM, and do not use any specific instructions. 28 28 29 29 The virtual address is 32 bits, and the physical address has up to 40 bits. It defines two types of pages (4 Kbytes pages, and 2 Mbytes pages). The page tables are mapped in memory and have a classical two level hierarchical structure. There is of course two separated TLB (Translation Look-aside Buffers) for instruction addresses and data addresses. … … 33 33 == 4. DHCCP cache coherence protocol == 34 34 35 The shared memory TSAR architecture implements the DHCCP protocol (Distributed Hybrid Cache Coherence Protocol). As it is not possible to monitor all simultaneous transaction in a distributed network on chip, the DHCCP protocol is 35 The shared memory TSAR architecture implements the DHCCP protocol (Distributed Hybrid Cache Coherence Protocol). As it is not possible to monitor all simultaneous transaction in a distributed network on chip, the DHCCP protocol is based on the global directory paradigm. 36 36 37 37 To simplify the scalability problem, the TSAR architecture benefits from the scalable bandwidth provided by the NoC technology and implements a WRITE-THROUGH policy between the distributed L1 caches and the distributed memory caches. This WRITE-THROUGH policy provides a tremendous simplification on the cache coherence protocol, as the memory is always up to date, and there is no exclusive ownership state for a modified cache line. In this approach, the memory controller (actually the memory caches) must register all cache line replicated in the various L1 caches, and send update or invalidate requests to all L1 caches that have a copy when a shared cache line is written. … … 45 45 The TSAR architecture requires a hierarchical two levels interconnect : each cluster must contain a local interconnect, and the communications between clusters relies on a global interconnect. 46 46 47 As described in [CacheCoherence the cache coherence section], the DHCCP protocol defines three classes of transactions that must use three separated interconnection networks : the D_network, used for the direct read/write transactions; the C_network, used for coherence transactions; the X 47 As described in [CacheCoherence the cache coherence section], the DHCCP protocol defines three classes of transactions that must use three separated interconnection networks : the D_network, used for the direct read/write transactions; the C_network, used for coherence transactions; the X_network, used to access the external memory in case of Miss on the memory cache. 48 48 49 49 The DSPIN network on chip (developed by the LIP6 laboratory) implements the D_network and the C_network. It has the requested 2D mesh topology, and provides the shared memory TSAR architecture a truly scalable bandwidth. It supports the VCI/OCP standard, and implements a logically “flat” address space. It is well suited to power consumption management, as it relies on the GALS (Globally Asynchronous, Locally Synchronous) approach : Both the voltage & the clock frequency can be independently adjusted in each cluster. It provides two fully separated virtual channels for the direct traffic and for the coherence traffic. It provides the broadcast service requested by the DHCCP protocol.
