| | 1 | == TLMDT Modeling for tightly interdependent architectures with several levels of interconnections == |
| | 2 | === 0. Introduction |
| | 3 | ''This document is still under development''. |
| | 4 | |
| | 5 | This TLMDT specification is strongly based on the [http://www.soclib.fr/trac/dev/wiki/WritingRules/Tlmt TLMDT for SOCLIB] one.[[BR]] |
| | 6 | Several rules are preserved : |
| | 7 | * Method used to model a VCI / PDES transaction (payload with extension / phase / time) |
| | 8 | * Global modeling of the VCI Initiator and VCI Target |
| | 9 | * Global description on the interconnect's work |
| | 10 | * PDES : activity message |
| | 11 | Some others are not : |
| | 12 | * PDES : null-message |
| | 13 | * PDES : token (not described in the link) |
| | 14 | * Interconnect's inner synchronisation mechanisms |
| | 15 | |
| | 16 | Another TLMDT specification is needed to prevent deadlocks and to greatly promote performance & parallelization with minor loss to precision on architecture that are not only composed of simple initiators and targets linked through a single network.[[BR]] |
| | 17 | List of components' behaviors which exists on TSAR and cannot be efficiently modeled without a new specification : |
| | 18 | * Multi-transactionnal initiators |
| | 19 | * Multiple networks on which a single component can (directly or not) be an initiator for several ports of an interconnect. |
| | 20 | * Components which are target and initiator at the same time. |
| | 21 | |
| | 22 | === 1. VCI Messages usage |
| | 23 | === 2. PDES Messages usage |
| | 24 | === 3. Efficient time modeling in a multi-transactionnal VCI Component |
| | 25 | === 4. VCI Initiator modeling |
| | 26 | === 5. VCI Target-Initiator (decoupled) modeling |
| | 27 | === 6. VCI Target-Initiator (coupled) modeling |
| | 28 | === 7. VCI Target modeling |
| | 29 | === 8. VCI Local Crossbar modeling |
| | 30 | === 9. VCI Global Crossbar modeling |
| | 31 | === 10. Proof of the deadlock free feature |
| | 32 | === 11. Locating the loss in precision |
