Changes between Version 11 and Version 12 of VirtualMemory

Timestamp:

Jun 29, 2009, 11:09:30 AM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -110 +110 @@
 
 Similarly, the L1 cache controller contains two separated hardware MMUs for instruction and data. Each MMU contains a 64 entries TLB (Translation Look-aside Buffer).
-These TLBs are implemented as set-associative caches (8 sets of 8 ways). Each entry in these TLBs can contain either a 4 Kbytes page descriptor, or a 2 Mbytes page descriptor.
+These TLBs are implemented as set-associative caches (16 sets of 4 ways). Each entry in these TLBs can contain either a 4 Kbytes page descriptor, or a 2 Mbytes page descriptor.
 
-For both data & instructions, the TSAR L1 caches use physical addresses (the tags contained in the directories are obtained from the physical addresses).
-The access to the L1 cache being a critical path, the TSAR MMU use a speculative approach to avoid to serialize the TLB access and the L1 cache access.
+[[Image(cache_tlb.png, nolink)]]
+
+For both data & instructions, the TSAR L1 caches use physical addresses : the cache directories are indexed by the physical addresses, and the tags contained in the directories are obtained from the physical addresses. The access to the L1 cache being a critical path, the TSAR MMU use a speculative approach to avoid to serialize the TLB access and the L1 cache access:
+ * After each TLB hit, the input VPN and the resulting PPN values are saved in two VPN_save & PPN_save registers. 
+ * During access (n), the PPN_save value, corresponding to access (n_1) is used to access the cache. Simultaneously, the cache controller checks that the VPN value is equal to the VPN_save value (no page change). 
+ * In case of TLB hit with a page change, the cache must be accessed twice, which means one cycle penalty.
+
 
 === 2.1 Generic MMU activation ===