Changes between Version 12 and Version 13 of VirtualMemory

Timestamp:

Jun 29, 2009, 12:35:34 PM (16 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -110 +110 @@
 
 Similarly, the L1 cache controller contains two separated hardware MMUs for instruction and data. Each MMU contains a 64 entries TLB (Translation Look-aside Buffer).
-These TLBs are implemented as set-associative caches (16 sets of 4 ways). Each entry in these TLBs can contain either a 4 Kbytes page descriptor, or a 2 Mbytes page descriptor.
+These TLBs are implemented as set-associative caches (16 sets of 4 ways). Each entry in these TLBs can contain either a 4 Kbytes page descriptor, or a 2 Mbytes page descriptor. The figure below illustrate the general structure of the TSAR L1 caches.
 
 [[Image(cache_tlb.png, nolink)]]
@@ -127 +127 @@
 === 2.2 Generic MMU exceptions ===
 
+The hardware MMU can signal exceptions by rising the general instruction_bus_error and data_bus_error signals (for an instruction or data accesss respectively). 
+The error type is written in the INS_ERROR_TYPE & DATA_ERROR_TYPE registers, as described below:
+
+|| Exeption type                              || code  || cause                                                         || severity ||
+||                                                       ||            ||                                                                    ||                      ||
+||MMU_PT1_UNMAPPED                ||            || Page fault on Table1 (invalid PTE)   || non fatal error ||
+||MMU_PT2_UNMAPPED                ||            || Page fault on Table 2 (invalid PTE)  || non fatal error ||
+||MMU_PRIVILEGE_VIOLATION         ||            ||Protected access in user mode         || user  error ||
+||MMU_WRITE_VIOLATION             ||            || Write access to a non write page             || user error ||
+||MMU_EXEC_VIOLATION              ||            || Exec access to a non exec page               || user error ||
+||MMU_UNDEFINED_XTN               ||            || Undefined external access address     || user error ||
+||MMU_PT1_ILLEGAL_ACCESS          ||            || Bus Error accès Table1                               || kernel error ||
+||MMU_PT2_ILLEGAL_ACCESS          ||            || Bus Error accès Table2                               || kernel error ||
+||MMU_CACHE_ILLEGAL_ACCESS ||            || Bus Error during the cache access      ||kernel error ||
+
+
 === 2.3 generic MMU registers mapping ===
 
-The software controlled following registers are the  by appending 
+The generic MMU contains a set of registers (or pseudo-registers) that can be accessed by operating system,
+through a dedicated MMU driver.
+In the case of the MIPS processor, these registers are implemented in coprocessor 2, and are accessed 
+using the ''mtc2'' (write) and ''mfc2'' (read) instructions.
+
+These registers are described below :
+
+|| register name               || index  || description                                                    || mode ||
+||                                         ||             ||                                                                         ||            ||
+|| MMU_PTPR                    ||             || Page Table Pointer Register                       || R/W   ||
+|| MMU_TLB_EN               ||             || Data & Inst TLBs Mode Register                || R/W   ||
+|| MMU_ICACHE_FLUSH   ||                    || Instruction Cache flush                          || W       ||
+|| MMU_DCACHE_FLUSH ||              || Data Cache flush                                         || W       ||
+|| MMU_ITLB_INVAL         ||             || Instruction TLB line invalidation                || W       ||
+|| MMU_DTLB_INVAL           ||             || Data TLB line Invalidation                                || W       ||
+|| MMU_ICACHE_INVAL   ||             || Instruction Cache line invalidation            || W       ||
+|| MMU_DCACHE_INVAL  ||             || Data Cache line invalidation                       || W       ||
+|| MMU_IETR                         ||             || Instruction Exception Type Register          || R/W  ||
+|| MMU_IBVAR                   ||             || Instruction Bad Virtual Address Register  || R/W  ||
+|| MMU_DETR                    ||             || Data Exception Type Register                    || R/W   ||
+|| MMU_DBVAR                 ||             || Data Bad Virtual Address Register             || R/W  || 
+