Changes between Version 18 and Version 19 of VirtualMemory
- Timestamp:
- Jul 1, 2009, 4:59:59 PM (15 years ago)
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VirtualMemory
v18 v19 1 1 [[PageOutline]] 2 2 3 = TSAR virtual memory=3 = TSAR MMU = 4 4 5 The TSAR MMU (Memory Management Unit) is an hardware component implemented in the L1 cache controller. This cache controller is a generic component that can be used with any single instruction issue, 32 bits processor. As any MMU, the generic TSAR MMU is in charge of the virtual to physical address translation, and perfoms 6 access right verifications. It implements a paginated virtual memory, supporting two page sizes : 4 Kbytes pages, and 2 Mbytes pages. 5 The TSAR MMU (Memory Management Unit) is an hardware component implemented in the L1 cache controller. This generic component can be used with any single instruction issue, 32 bits processor. 7 6 8 7 [[Image(generic_mmu.png, nolink)]] … … 10 9 As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches, 11 10 sharing the same physical access to the VCI/OCP interconnect. These L1 caches use physical addresses. 12 Similarly, the L1 cache controller contains two separated hardware MMUs for instruction and data. 11 As any MMU, the generic TSAR MMU is in charge of the virtual to physical address translation, and perfoms 12 access right verifications. It implements a paginated virtual memory, supporting two page sizes : 4 Kbytes pages, and 2 Mbytes pages. 13 Therefore, the TSAR MMU contains two separated hardware TLBs for instruction and data. 13 14 In order to be independent on the processor core choice, the TLB MISS are handled by an hardwired Finite State Machine (called a Table Walk), without any software action. 14 15 … … 100 101 101 102 102 == 2. Generic MMU ==103 == 2. Generic MMU architecture == 103 104 104 105 The generic MMU is implemented as an hardware component in the L1 cache controller. … … 178 179 || MMU_DBVAR || 14 || Data Bad Virtual Address Register || R || 179 180 180 181 182 183 181 == 3. I/O MMU == 184 182
