Changes between Version 20 and Version 21 of VirtualMemory

Timestamp:

Jul 3, 2009, 12:00:42 PM (17 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -100 +100 @@
 The PPN2 value (28 bits) must be concatened with the page offset (12 bits) to build the 40 bits physical address. 
 
-
-== 2. Generic MMU architecture ==
+== 2.  MMU/processor interface ==
+
+In order to be used withthe various (32 bits) processor cores available in the SoCLib library, the TSAR generic MMU respects the following processor/MMU interface:
+
+=== 2.1  Instruction MMU interface ===
+
+The Instruction MMU interface is defined by the following signals :
+
+{{{
+struct InstructionRequest {
+        bool valid;
+        uint30_t addr;
+        enum ExecMode mode;
+    };
+struct InstructionResponse {
+        bool valid;
+        bool error;
+        uint32_t instruction;
+    };
+}}}
+
+The  addr virtual address is a 32 bits word adress. It is coded on 30 bits. 
+
+The possible values for the Execution Mode are defined below :
+
+|| ExecMode || Value ||
+||                    ||            ||
+|| Hyper        || *1       ||
+|| Kernel       || 00       ||
+|| User          || 10        ||
+
+=== 2.2 Data MMU interface ===
+
+The Data MMU interface is defined by the following signals :
+
+{{{
+struct DataRequest {
+        bool valid;
+        uint30_t addr;
+        uint32_t wdata;
+        enum DataOperationType type;
+        uint4_t be;
+        enum ExecMode mode;
+    };
+struct DataResponse {
+        bool valid;
+        bool error;
+        uint32_t rdata;
+    };
+}}}
+
+The  addr virtual address is a 32 bits word adress. It is coded on 30 bits. 
+
+The wdata field is only significant for be-masked bytes:
+
+ * wdata[7:0] is at ![addr], masked by be[0]
+ * wdata[15:8] is at [addr+1], masked by be[1]
+ * wdata[23:16] is at [addr+2], masked by be[2]
+ * wdata[31:24] is at [addr+3], masked by be[3]
+
+The possible values for the execution mode are the same as for the instructions.
+
+The possible values for the OperationType field are defined below :
+
+|| Data.OperationType || R X L S Z  || semantic    ||
+||                                     ||                      ||
+|| DATA_READ              || 1 0 0 0 0 || load 32 bits from memory address space ||
+|| DATA_WRITE             || 0 0 0 0 0 || store 32 bits to memory adress space ||
+|| DATA_LL                    || 1 0 1 0 0 || load 32 bits from memory address space with reservation ||
+|| DATA_SC                   || 0 0 1 0 0 || conditionnal store 32 bits to memory address space ||
+|| XTN_READ                 || 1 1 0 0 0 || load 32 bits from MMU register ||
+|| XTN_WRITE                || 0 1 0 0 0 || store 32 bits to MMU register ||
+|| DATA_LLRST             || 0 0 0 0 1 || reset a previous LL reservation ||
+|| DATA_SYNC              || 0 0 0 1 0 || execute all pending write requests ||
+
+Note : Instruction request & data requests are independent :  the processor can issue simultaneous 
+data & instruction requests that have  different execution modes. 
+
+In case of access to an eXTerNal register (XTN_READ or XTN_WRITE) the MMU register is identified by the Data.Address field. 
+(see section 3).
+
+== 3. MMU architecture ==
 
 The generic MMU is implemented as an hardware component in the L1 cache controller.