Changes between Version 21 and Version 22 of VirtualMemory
- Timestamp:
- Jul 3, 2009, 12:09:41 PM (16 years ago)
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VirtualMemory
v21 v22 5 5 The TSAR MMU (Memory Management Unit) is an hardware component implemented in the L1 cache controller. This generic component can be used with any single instruction issue, 32 bits processor. 6 6 7 As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches, 8 sharing the same physical access to the VCI/OCP interconnect. These L1 caches use physical addresses. 9 As any MMU, the generic TSAR MMU is in charge of the virtual to physical address translation, and perfoms 10 access right verifications. It implements a paginated virtual memory, supporting two page sizes : 4 Kbytes pages, and 2 Mbytes pages. 11 Therefore, the TSAR MMU contains two separated hardware TLBs for instruction and data. 7 As the processor core can issue two simultaneous instruction and data requests, there is actually two separated MMUs for DATA data and instructions. 8 These two MMUs share the same physical access to the VCI/OCP interconnect. 9 Each MMU contains a set-associative cache and a TLB (Translation look-aside buffer), that is in charge of the virtual to physical address translation, and perfoms 10 access right verifications. 11 12 The Tsar generic MMU implements a paginated virtual memory, supporting two page sizes : 4 Kbytes pages, and 2 Mbytes pages. 12 13 In order to be independent on the processor core choice, the TLB MISS are handled by an hardwired Finite State Machine (called a Table Walk), without any software action. 13 14 14 15 [[Image(generic_mmu.png, nolink)]] 15 16 16 == 1. Page Table Organisation==17 == 1. Virtual Memory == 17 18 18 19 The TSAR architecture defines two page sizes : 4 Kbytes pages, and 2 Mbytes pages. … … 20 21 The physical address space is limited to 1 Tbytes (40 bits physical addresses). 21 22 The page table are build by the operating system, and are stored in the main memory. 23 Each execution context (such as an UNIX process) has is own page table. 22 24 23 25 === 1.1 Two levels Page Table structure === … … 259 261 || MMU_DBVAR || 14 || Data Bad Virtual Address Register || R || 260 262 261 == 3. I/O MMU == 262 263 To be defined... 264 263 264
