Changes between Version 23 and Version 24 of VirtualMemory


Ignore:
Timestamp:
Jul 3, 2009, 1:45:42 PM (15 years ago)
Author:
alain
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • VirtualMemory

    v23 v24  
    33= TSAR MMU =
    44
    5 The TSAR MMU (Memory Management Unit) is an hardware component implemented in the L1 cache controller. This generic component can be used with any  single instruction issue, 32 bits processor.
    6 
    7 As the processor core can issue two simultaneous instruction and data requests, there is actually two separated MMUs for DATA data and instructions.
     5The TSAR MMU (Memory Management Unit) is an hardware component implemented as a L1 cache controller. This generic component can be used with any  single instruction issue, 32 bits processor.
     6
     7As the processor core can issue two simultaneous instruction and data requests, there is actually two separated MMUs for data and instructions.
    88These two MMUs share the same physical access to the VCI/OCP interconnect.
    99Each MMU contains a set-associative cache and a TLB (Translation look-aside buffer), that is in charge of the virtual to physical address translation, and perfoms