Changes between Version 26 and Version 27 of VirtualMemory

Timestamp:

Jul 15, 2009, 6:41:27 PM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -245 +245 @@
 These registers are described below :
 
-|| register name               || index  || description                                                    || mode ||
-||                                         ||             ||                                                                         ||            ||
-|| MMU_PTPR                    ||    0       || Page Table Pointer Register                       || R/W   ||
-|| MMU_MODE                 ||    1       || Data & Inst TLBs Mode Register                || R/W   ||
-|| MMU_ICACHE_FLUSH   ||           2       || Instruction Cache flush                           || W       ||
-|| MMU_DCACHE_FLUSH ||     3       || Data Cache flush                                          || W       ||
-|| MMU_ITLB_INVAL         ||    4       || Instruction TLB line invalidation                || W     ||
-|| MMU_DTLB_INVAL           ||   5        || Data TLB line Invalidation                         || W      ||
-|| MMU_ICACHE_INVAL   ||    6       || Instruction Cache line invalidation            || W     ||
-|| MMU_DCACHE_INVAL  ||    7      || Data Cache line invalidation                       || W     ||
-|| MMU_IETR                         ||  11      || Instruction Exception Type Register          || R      ||
-|| MMU_DETR                    ||  12      || Data Exception Type Register                       || R      ||
-|| MMU_IBVAR                   ||  13      || Instruction Bad Virtual Address Register  || R      ||
-|| MMU_DBVAR                 ||  14      || Data Bad Virtual Address Register             || R      || 
-
-
-
+|| register name                      || index  || description                                                    || mode ||
+||                                                ||             ||                                                                         ||            ||
+|| MMU_PTPR                           ||    0       || Page Table Pointer Register                       || R/W   ||
+|| MMU_MODE                        ||    1       || Data & Inst TLBs Mode Register                || R/W   ||
+|| MMU_ICACHE_FLUSH          ||    2      || Instruction Cache flush                            || W       ||
+|| MMU_DCACHE_FLUSH        ||      3       || Data Cache flush                                          || W       ||
+|| MMU_ITLB_INVAL                ||    4       || Instruction TLB line invalidation                || W     ||
+|| MMU_DTLB_INVAL                  ||   5        || Data TLB line Invalidation                          || W      ||
+|| MMU_ICACHE_INVAL          ||    6       || Instruction Cache line invalidation            || W     ||
+|| MMU_DCACHE_INVAL         ||    7      || Data Cache line invalidation                       || W     ||
+|| MMU_ICACHE_PREFETCH   ||    8      || Instruction Cache line prefetch                  || W     ||
+|| MMU_DCACHE_PREFETCH ||    9       || Data Cache line prefetch                             || W     ||
+|| MMU_SYNC                           ||  10      || Complete pending writes                            || W     ||
+|| MMU_IETR                                ||  11      || Instruction Exception Type Register          || R      ||
+|| MMU_DETR                           ||  12      || Data Exception Type Register                        || R      ||
+|| MMU_IBVAR                          ||  13      || Instruction Bad Virtual Address Register  || R      ||
+|| MMU_DBVAR                        ||  14      || Data Bad Virtual Address Register             || R      || 
+
+
+