Changes between Version 27 and Version 28 of VirtualMemory

Timestamp:

Jul 15, 2009, 6:52:14 PM (16 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -184 +184 @@
 == 3. MMU architecture ==
 
-The generic MMU is implemented as an hardware component in the L1 cache controller. 
-
-As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches,
-sharing the same physical access to the VCI/OCP interconnect. These cache are set associative, and have a total capacity of 16 Kbytes :
+The generic MMU is implemented in the L1 cache controller. 
+
+As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches, sharing the same physical access to the VCI/OCP interconnect. These cache are set associative, and have a total capacity of 16 Kbytes :
  * cache line width = 64 bytes
  * number of associative sets = 64 sets
@@ -210 +209 @@
 
 
-=== 2.1 Generic MMU activation ===
-
-After general RESET, both the L1 caches and the generic MMU are desactivated : As long as the MMU is not activated, the 32 bits virtual address is simply extended to 40 bits,
-and directly used as a physical address. As long as the caches are not activated, all access are handled as uncached by the cache controller.
-
-The instruction cache, the data cache, the instruction MMU and the data MMU can be separately activated by the software, by writing in the MMU_MODE register, using the
-MMU driver.
-
-=== 2.2 Generic MMU exceptions ===
+=== 3.1  MMU activation ===
+
+After general RESET, the the MMU is desactivated : As long as the MMU is not activated, the 32 bits virtual address is simply extended to 40 bits (for both data and instructions), by appending 8 nul bits and directly used as a physical address. As long as the caches are not activated, all read requests are considered ''uncached'' by the cache controller.
+
+The instruction cache, the data cache, the instruction MMU and the data MMU can be separately activated by the software, by writing in the MMU_MODE register.
+
+=== 3.2 Generic MMU exceptions ===
 
 The hardware MMU can signal exceptions by rising the general instruction_bus_error and data_bus_error signals (for an instruction or data accesss respectively). 
@@ -236 +233 @@
 
 
-=== 2.3 generic MMU registers mapping ===
+=== 3.3 generic MMU registers mapping ===
 
 The generic MMU contains a set of registers (or pseudo-registers) that can be accessed by operating system,