186 | | The generic MMU is implemented as an hardware component in the L1 cache controller. |
187 | | |
188 | | As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches, |
189 | | sharing the same physical access to the VCI/OCP interconnect. These cache are set associative, and have a total capacity of 16 Kbytes : |
| 186 | The generic MMU is implemented in the L1 cache controller. |
| 187 | |
| 188 | As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches, sharing the same physical access to the VCI/OCP interconnect. These cache are set associative, and have a total capacity of 16 Kbytes : |
212 | | === 2.1 Generic MMU activation === |
213 | | |
214 | | After general RESET, both the L1 caches and the generic MMU are desactivated : As long as the MMU is not activated, the 32 bits virtual address is simply extended to 40 bits, |
215 | | and directly used as a physical address. As long as the caches are not activated, all access are handled as uncached by the cache controller. |
216 | | |
217 | | The instruction cache, the data cache, the instruction MMU and the data MMU can be separately activated by the software, by writing in the MMU_MODE register, using the |
218 | | MMU driver. |
219 | | |
220 | | === 2.2 Generic MMU exceptions === |
| 211 | === 3.1 MMU activation === |
| 212 | |
| 213 | After general RESET, the the MMU is desactivated : As long as the MMU is not activated, the 32 bits virtual address is simply extended to 40 bits (for both data and instructions), by appending 8 nul bits and directly used as a physical address. As long as the caches are not activated, all read requests are considered ''uncached'' by the cache controller. |
| 214 | |
| 215 | The instruction cache, the data cache, the instruction MMU and the data MMU can be separately activated by the software, by writing in the MMU_MODE register. |
| 216 | |
| 217 | === 3.2 Generic MMU exceptions === |