Changes between Version 27 and Version 28 of VirtualMemory


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Timestamp:
Jul 15, 2009, 6:52:14 PM (15 years ago)
Author:
alain
Comment:

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  • VirtualMemory

    v27 v28  
    184184== 3. MMU architecture ==
    185185
    186 The generic MMU is implemented as an hardware component in the L1 cache controller.
    187 
    188 As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches,
    189 sharing the same physical access to the VCI/OCP interconnect. These cache are set associative, and have a total capacity of 16 Kbytes :
     186The generic MMU is implemented in the L1 cache controller.
     187
     188As the processor core can issue two simultaneous instruction and data requests, there is actually two separated data and instructions caches, sharing the same physical access to the VCI/OCP interconnect. These cache are set associative, and have a total capacity of 16 Kbytes :
    190189 * cache line width = 64 bytes
    191190 * number of associative sets = 64 sets
     
    210209
    211210
    212 === 2.1 Generic MMU activation ===
    213 
    214 After general RESET, both the L1 caches and the generic MMU are desactivated : As long as the MMU is not activated, the 32 bits virtual address is simply extended to 40 bits,
    215 and directly used as a physical address. As long as the caches are not activated, all access are handled as uncached by the cache controller.
    216 
    217 The instruction cache, the data cache, the instruction MMU and the data MMU can be separately activated by the software, by writing in the MMU_MODE register, using the
    218 MMU driver.
    219 
    220 === 2.2 Generic MMU exceptions ===
     211=== 3.1  MMU activation ===
     212
     213After general RESET, the the MMU is desactivated : As long as the MMU is not activated, the 32 bits virtual address is simply extended to 40 bits (for both data and instructions), by appending 8 nul bits and directly used as a physical address. As long as the caches are not activated, all read requests are considered ''uncached'' by the cache controller.
     214
     215The instruction cache, the data cache, the instruction MMU and the data MMU can be separately activated by the software, by writing in the MMU_MODE register.
     216
     217=== 3.2 Generic MMU exceptions ===
    221218
    222219The hardware MMU can signal exceptions by rising the general instruction_bus_error and data_bus_error signals (for an instruction or data accesss respectively).
     
    236233
    237234
    238 === 2.3 generic MMU registers mapping ===
     235=== 3.3 generic MMU registers mapping ===
    239236
    240237The generic MMU contains a set of registers (or pseudo-registers) that can be accessed by operating system,