262 | | |
263 | | |
| 262 | The generic MMU Mode Register has four bits and these 16 values are described as below : |
| 263 | |
| 264 | || MODE3 || MODE2 || MODE1 || MODE0 || description || |
| 265 | || (INS TLB) || (DATA TLB) || (INS CACHE) || (DATA CACHE) || || |
| 266 | || 0 || 0 || 0 || 0 || TLBs and caches deactivated || |
| 267 | || 0 || 0 || 0 || 1 || TLBs and instruction cache deactivated, data cache actived || |
| 268 | || 0 || 0 || 1 || 0 || TLBs and data cache deactivated, instruction cache actived || |
| 269 | || 0 || 0 || 1 || 1 || TLBs deactivated, instruction and data cache actived || |
| 270 | || 0 || 1 || 0 || 0 || Instruction TLB and caches deactivated, data TLB actived || |
| 271 | || 0 || 1 || 0 || 1 || Instruction TLB and instruction cache deactivated, data TLB and data cache actived || |
| 272 | || 0 || 1 || 1 || 0 || Instruction TLB and data cache deactivated, data TLB and instruction cache actived || |
| 273 | || 0 || 1 || 1 || 1 || Instruction TLB deactivated, data TLB and caches actived || |
| 274 | || 1 || 0 || 0 || 0 || Data TLB and caches deactivated, instruction TLB actived || |
| 275 | || 1 || 0 || 0 || 1 || Data TLB and instruction cache deactivated, instruction TLB and data cache actived || |
| 276 | || 1 || 0 || 1 || 0 || Data TLB and data cache deactivated, instruction TLB and instruction cache actived || |
| 277 | || 1 || 0 || 1 || 1 || Data TLB deactivated, instruction TLB and caches actived || |
| 278 | || 1 || 1 || 0 || 0 || Caches deactivated, TLBs actived || |
| 279 | || 1 || 1 || 0 || 1 || Instruction cache deactivated, TLBs and data cache actived || |
| 280 | || 1 || 1 || 1 || 0 || Data cache deactivated, TLBs and instruction cache actived || |
| 281 | || 1 || 1 || 1 || 1 || TLBs and caches actived || |