Changes between Version 29 and Version 30 of VirtualMemory

Timestamp:

Jul 31, 2009, 6:23:32 PM (16 years ago)

Author:

gao

Comment:

--

VirtualMemory

@@ -245 +245 @@
 ||                                                ||             ||                                                                         ||            ||
 || MMU_PTPR                           ||    0       || Page Table Pointer Register                       || R/W   ||
-|| MMU_MODE                        ||    1       || Data & Inst TLBs Mode Register                || R/W   ||
+|| MMU_MODE                        ||    1       || Data & Inst TLBs and caches Mode Register                || R/W   ||
 || MMU_ICACHE_FLUSH          ||    2      || Instruction Cache flush                            || W       ||
 || MMU_DCACHE_FLUSH        ||      3       || Data Cache flush                                          || W       ||
@@ -260 +260 @@
 || MMU_DBVAR                        ||  14      || Data Bad Virtual Address Register             || R      || 
 
-The generic MMU Mode Register has four bits and these 16 values are described as below :
+The MMU Mode Register has four bits and these 16 values are described as below :
 
 ||   MODE3   ||    MODE2   ||     MODE1   ||     MODE0    ||    description                                                                     ||
 || (INS TLB) || (DATA TLB) || (INS CACHE) || (DATA CACHE) ||                                                                                    ||
+||           ||            ||             ||              ||                                                                                    ||
 ||     0     ||      0     ||      0      ||       0      || TLBs and caches deactivated                                                        ||
 ||     0     ||      0     ||      0      ||       1      || TLBs and instruction cache deactivated, data cache actived                         ||
 ||     0     ||      0     ||      1      ||       0      || TLBs and data cache deactivated, instruction cache actived                         ||
-||     0     ||      0     ||      1      ||       1      || TLBs deactivated, instruction and data cache actived                               ||
+||     0     ||      0     ||      1      ||       1      || TLBs deactivated, caches actived                                                   ||
 ||     0     ||      1     ||      0      ||       0      || Instruction TLB and caches deactivated, data TLB actived                           ||
 ||     0     ||      1     ||      0      ||       1      || Instruction TLB and instruction cache deactivated, data TLB and data cache actived ||