Changes between Version 33 and Version 34 of VirtualMemory


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Timestamp:
Sep 9, 2009, 5:16:33 PM (15 years ago)
Author:
alain
Comment:

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  • VirtualMemory

    v33 v34  
    6767If the entry is a PTE1, the PPN1 value (19 bits) must be concatened with the page offset (21 bits) to build the 40 bits physical address.
    6868
    69 If the entry is a PTD1, the PTBA value (28 bits) must be left-shifted by 12 bits to define the base address of the level 2 page table. The page table being aligned in memory, the 12 LSB bits of this base address have a 0 value.
     69If the entry is a PTD1, the PTBA value (28 bits) must be left-shifted by 12 bits to define the base address of the level 2 page table. The page table being aligned in memory, the 12 LSB bits of this base address have a 0 value.
     70
     71The ''reserved'' bits are are specified for future hardware extensions, and must not be used by the operating system.
    7072
    7173=== 1.3 Second Level Page Table Entry Format ===
    … …  
    7577
    7678 * PTE2 first word  :
    77 ||V||T||L||R||C||W||X||U||G||D|| reserved (22 bits) ||
     79||V||T||L||R||C||W||X||U||G||D|| reserved (14 bits) || soft (8 bits) ||
    7880
    7981 * PTE2 second word :
    … …  
    100102These page table updates use atomic access (LL/SC).
    101103
    102 The PPN2 value (28 bits) must be concatened with the page offset (12 bits) to build the 40 bits physical address.
     104The PPN2 value (28 bits) must be concatened with the page offset (12 bits) to build the 40 bits physical address.
     105 
     106The ''reserved'' bits are are specified for future hardware extensions, and must not be used by the operatin system.
     107The ''soft'' bits can be used by the operating system, will not be modified by the hardware MMU.
    103108
    104109== 2.  MMU/processor interface ==
    … …  
    229234||MMU_WRITE_PT1_ILLEGAL_ACCESS    || 0x0040 || Write access : Bus Error in Table1 access                      || kernel error ||
    230235||MMU_WRITE_PT2_ILLEGAL_ACCESS    || 0x0080 || Write access : Bus Error in Table2 access                      || kernel error ||
    231 ||MMU_WRITE_CACHE_ILLEGAL_ACCESS     || 0x0100 || Write access : Bus Error during the cache access        ||kernel error ||
     236||MMU_WRITE_DATA_ILLEGAL_ACCESS     || 0x0100 || Write access : Bus Error during the cache access        ||kernel error ||
    232237||MMU_READ_PT1_UNMAPPED                   || 0x1001 || Read  access : Page fault on Table1 (invalid PTE)               || non fatal error ||
    233238||MMU_READ_PT2_UNMAPPED                   || 0x1002 || Read  access : Page fault on Table 2 (invalid PTE)       || non fatal error ||
    … …  
    237242||MMU_READ_PT1_ILLEGAL_ACCESS             || 0x1040 || Read  access : Bus Error in Table1 access                    || kernel error ||
    238243||MMU_READ_PT2_ILLEGAL_ACCESS             || 0x1080 || Read  access : Bus Error in Table2 access                    || kernel error ||
    239 ||MMU_READ_CACHE_ILLEGAL_ACCESS     || 0x1100 || Read  access : Bus Error during the cache access      ||kernel error ||
     244||MMU_READ_DATA_ILLEGAL_ACCESS     || 0x1100 || Read  access : Bus Error during the cache access      ||kernel error ||
    240245
    241246