Changes between Version 36 and Version 37 of VirtualMemory

Timestamp:

Sep 11, 2009, 1:48:48 PM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -275 +275 @@
 
 The '''MMU_PTPR''' register contains the base address of the currently used first level page table.
-As this base address is aligned on a 8 Kbytes boundary, and we want to support (up to) 40 bits
-physical addresses, the PTPR register contains only the 27 MSB bits of the base address :
+The PTPR is a 32 bits register, and the physical address can be (up to) 40 bits.
+As the base address is aligned on a 8 Kbytes boundary, the PTPR register contains only the 27 MSB bits of the base address :
 
 || 00000 || BASE_ADDRESS[39:13] ||
@@ -304 +304 @@
 The '''MMU_PARAMS''' register define the instruction and data caches & TLBs characteristics :
 
-  ||WTD||STD||WCD||SCD||WTI||STI||WCII||SCI||NBL||
+  ||WTD||STD||WCD||SCD||WTI||STI||WCI||SCI||NBL||
  * WTD (3 bits) : Ln(number of associative ways for the Data TLB)
  * STD (4 bits) : Ln(number of sets for the Data TLB)