Changes between Version 3 and Version 4 of VirtualMemory


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Timestamp:
Jun 27, 2009, 3:58:23 PM (16 years ago)
Author:
alain
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  • VirtualMemory

    v3 v4  
    2727-       The PTPR register (located in the generic MMU, and initialised by  the OS at each context switch) contains actually the 26 MSB bits  of the first level page table base address. It must be extended (left-shifted) to 36 bits by the hardware.
    2828
    29 === 1.2 Second Level Page Table Entry Format ===
     29=== 1.2 First Level Page Table Entry Format ===
    3030
    31 Each entry in a second level page table is a 64 bits word containing a 4K bytes page descriptor (Called PTE2) :
     31Each entry in a first level page table can contain either a 2M bytes page descriptor (called PTE1), or a second level  page table descriptor (called PTD1).
     32It is implemented as a single 32 bits word :
    3233
    33  * PTE2[31:0] :
    34 ||V||T||L||R||C||W||X||U||G||D||              22 bits reserved        ||
     34* PTE1 :
     35||V||T||L||R||C||W||X||U||G||D|| reserved (3 bits) || PPN1 (19 bits) ||
    3536
    36  * PTE2[63:32] :
    37 || 4 bits reserved ||            PPN2                       (28 bits)              ||
     37 * PTD1
     38||V||T|| reserved (2 bits) ||            PTBA                      (28 bits)              ||
    3839
    39 The PTE2 fields are defined as follows :
     40The various fields are defined as follows :
    4041 
    41 || PPN2 || Physical Page Number  || 28 bits : Concatened to the page offset to build the 40 bits address ||
     42|| V            || Valid bit                              || Valid entry when 1 (set by the OS) ||
     43|| T            || Type bit                            || PTD1 when 1 (set by the OS) ||
     44|| L            || Local access bit                 || Used by the OS for page replacement (set by the hardware) ||
     45|| R            || Remote access        bit            || Used by the OS for page replacement (set by the hardware) ||
     46|| C            || Cachable bit                       || The page is cachable in the L1 cache when 1 (set by the OS) ||
     47|| W            || Writable bit                         || The page is writable when 1 (set by the OS) ||
     48|| X            || eXecutable bit                    || The page can contain instructions when 1 (set by the OS) ||
     49|| U            || User bit                                || The page is accessible in user mode when 1 (set by the OS) ||
     50|| G            || Global       bit                             || Entry not invalidated in TLB flush when 1 (set by the OS) ||
     51|| D            || Dirty bit                                || The page has been modified when 1 (set by the hardware) ||
     52|| PPN1 || Physical Page Number       || Concatened to the page offset  to build the physical address ||
     53|| PTBA || Page Table Base Address  || Second level page table base address ||
     54
     55The L, R, D bits are used by the operating system to implement the page replacement policy.
     56 * The D bit is set by the hardware, when a page is written and when it is not already set, using an atomic access (LL/SC).
     57 * The L  bit is set by the hardware, when the page is accessed by a local processor or coprocessor, after a TLB miss, and when it is not already set.
     58 * The R  bit is set by the hardware, when the page is accessed by a remote processor or coprocessor, after a TLB miss, and when it is not already set.
     59These page table updates use atomic access (LL/SC).
     60
     61If the entry is a PTE1, the PPN1 value (19 bits) must be concatened with the page offset (21 bits) to build the 40 bits physical address.
     62
     63If the entry is a PTD1, the PTBA value (28 bits) must be left-shifted by 12 bits to define the base address of the level 2 page table. The page table being aligned in memory, the 12 LSB bits of this base address have a 0 value.
     64
     65=== 1.3 Second Level Page Table Entry Format ===
     66
     67Each entry in a second level page table  contains a 4K bytes page descriptor (called PTE2).
     68It is implemented as two 32 bits words: the first word contains the flags; the second word contains the 28 bits physical page number (PPN2).
     69
     70 * PTE2 first word  :
     71||V||T||L||R||C||W||X||U||G||D|| reserved (22 bits) ||
     72
     73 * PTE2 second word :
     74|| reserved (4 bits) ||            PPN2                       (28 bits)              ||
     75
     76The various fields are defined as follows :
     77 
    4278|| V            || Valid bit                          || Valid entry when 1 (set by the OS) ||
    43 || T            || Type bit                        || PTD when 1 / Must be 0 for a PTE2 (set by the OS) ||
     79|| T            || Type bit                        || Must be 0 for a PTE2 (set by the OS) ||
    4480|| L            || Local access bit             || Used by the OS for page replacement (set by the hardware) ||
    4581|| R            || Remote access        bit        || Used by the OS for page replacement (set by the hardware) ||
    … …  
    5086|| G            || Global       bit                        || Entry not invalidated in TLB flush when 1 (set by the OS) ||
    5187|| D            || Dirty bit                          || The page has been modified when 1 (set by the hardware) ||
     88|| PPN2 || Physical Page Number  || Concatened to the page offset to build the 40 bits address ||
    5289
     90The L, R, D bits are used by the operating system to implement the page replacement policy.
     91 * The D bit is set by the hardware, when a page is written and when it is not already set, using an atomic access (LL/SC).
     92 * The L  bit is set by the hardware, when the page is accessed by a local processor or coprocessor, after a TLB miss, and when it is not already set.
     93 * The R  bit is set by the hardware, when the page is accessed by a remote processor or coprocessor, after a TLB miss, and when it is not already set.
     94These page table updates use atomic access (LL/SC).
    5395
    54 The L, R, D bits are used by the operating system to implement the page replacement policy. The D bit is set by the hardware, when a page is written and when it is not already set, using an atomic access (LL/SC).
    55 The L & R bits are set by the hardware, when the page is accessed after a TLB miss, and when it is not already set, using an atomic access (LL/SC).
     96The PPN2 value (28 bits) must be concatened with the page offset (12 bits) to build the 40 bits physical address.
    5697
    57 === 1.3 First Level Page Table Entry Format ===
    58 
    59 Each entry in a first level page table is a 32 bits word containing either a 2M bytes page descriptor (called PTE1), or a second level  page table descriptor (called PTD1) :
    60 
    61 
    62 
    63 
    64 
    65 
    66 
    67 
    68 
    69 
    70 If the entry is a PTE1, the PPN1 value (19 bits) must be concatened with the page offset (21 bits) to build the 40 bits physical address. The (V, T, L, R, C, W, X, U, G, D) bits have the same meaning as in a PTE2.
    71 
    72 If the entry is a PTD1, PTBA is the Page Table Base Address. The PTBA value (28 bits) must be left-shifted by 12 bits to define the base address of the level 2 page table. The page table being aligned in memory, the 12 LSB bits of this address have a 0 value.
    7398
    7499== 2. Generic MMU ==