271 | | || MMU_IBVAR || 13 || Instruction Bad Virtual Address Register || R || |
272 | | || MMU_DBVAR || 14 || Data Bad Virtual Address Register || R || |
273 | | || MMU_PARAMS || 15 || Caches & TLBs hardware parameters || R || |
274 | | || MMU_RELEASE || 16 || Generic MMU release number || R || |
275 | | || MMU_ |
| 271 | || MMU_IBVAR || 13 || Instruction Bad Virtual Address Register || R || |
| 272 | || MMU_DBVAR || 14 || Data Bad Virtual Address Register || R || |
| 273 | || MMU_PARAMS || 15 || Caches & TLBs hardware parameters || R || |
| 274 | || MMU_RELEASE || 16 || Generic MMU release number || R || |
| 275 | || MMU_WORD_LO || 17 || Lowest part of a double word || R/W || |
| 276 | || MMU_WORD_HI || 18 || Highest part of a double word || R/W || |
| 277 | || MMU_DOUBLE_LL || 21 || Double word linked load || W || |
| 278 | || MMU_DOUBLE_SC || 21 || Double word store conditional || W || |
| 279 | || MMU_ICACHE_PA_INV || 19 || Instruction cache inval physical adressing || W || |
| 280 | || MMU_DCACHE_PA_INV || 20 || Data cache inval physical addressing || W || |
298 | | === 3.3.4 MMU_ITLB_INVAL & MMU_DTLB_INVAL === |
299 | | |
300 | | The value written in the 32 bits '''MMU_ITLB_INVAL''' register (resp. '''MMU_DTLB_INVAL''' register) is interpreted as a virtual address. If the instruction TLB (resp. the data TLB) contains an entry corresponding to this address, this entry is invalidated. |
301 | | |
302 | | === 3.3.5 MMU_ICACHE_INVAL & MMU_DCACHE_INVAL === |
303 | | |
304 | | The value written in the 32 bits '''MMU_ICACHE_INVAL''' register (resp. '''MMU_DCACHE_INVAL''' register) is interpreted as a virtual address. This address is translated to a physical address. If the instruction cache (resp. the data cache) contains an entry corresponding to this address, this entry is invalidated. |
305 | | |
306 | | === 3.3.6 MMU_ICACHE_PREFETCH & MMU_DCACHE_PREFETCH === |
| 303 | ==== 3.3.4 MMU_ITLB_INVAL & MMU_DTLB_INVAL ==== |
| 304 | |
| 305 | The value written in the 32 bits '''MMU_ITLB_INVAL''' register (resp. '''MMU_DTLB_INVAL''' register) is interpreted as a virtual address. If the instruction TLB (resp. the data TLB) contains an entry corresponding to this address, this entry is invalidated. This is a blocking request for the processor. |
| 306 | |
| 307 | ==== 3.3.5 MMU_ICACHE_INVAL & MMU_DCACHE_INVAL ==== |
| 308 | |
| 309 | The value written in the 32 bits '''MMU_ICACHE_INVAL''' register (resp. '''MMU_DCACHE_INVAL''' register) is interpreted as a virtual address. This address is translated to a physical address. If the instruction cache (resp. the data cache) contains an entry corresponding to this address, this entry is invalidated. This is a blocking request for the processor. |
| 310 | |
| 311 | ==== 3.3.6 MMU_ICACHE_PREFETCH & MMU_DCACHE_PREFETCH ==== |
309 | | |
310 | | === 3.3.x MMU_PARAMS === |
| 314 | This is a non-blocking request for the processor. |
| 315 | |
| 316 | ==== 3.3.7 MMU_SYNC ==== |
| 317 | |
| 318 | Writing any value in this '''MMU_SYNC''' register will force execution of posted write requests. |
| 319 | This is a blocking request for the processor. |
| 320 | |
| 321 | ==== 3.3.8 MMU_IETR & MMU_DETR ==== |
| 322 | |
| 323 | MMU exceptions are reported in these two registers, as described in section 3.2. |
| 324 | |
| 325 | ==== 3.3.9 MMU_IBVAR & MMU_DBVAR ==== |
| 326 | |
| 327 | Faulty virtual adresses will be written in these two registers. |
| 328 | |
| 329 | ==== 3.3.10 MMU_PARAMS ==== |
| 350 | |
| 351 | ==== 3.3.12 MMU_WORD_HI & MMU_WORD_LO ==== |
| 352 | |
| 353 | The two 32 bits '''MMU_DOUBLE_HI''' & MMU_DOUBLE_LO''' registers implement a double word data storage. |
| 354 | They are used to support cache line invalidation in physical adressing (section 3.3.15), and to support |
| 355 | double words LL & SC accesses (section 3.3.13 & section 3.3.14). |
| 356 | |
| 357 | ==== 3.3.13 MMU_DOUBLE_LL ==== |
| 358 | |
| 359 | The value written in the '''MMU_DOUBLE_LL''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Linked Load transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The read value is written in the MMU_WORD_HI & MMU_WORD_LO registers. This is a blocking transaction for the processor. |
| 360 | |
| 361 | ==== 3.4.14 MMU_DOUBLE_SC ==== |
| 362 | |
| 363 | The value written in the'''MMU_DOUBLE_SC''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Store Conditionnal transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The transmitted data are the values stored in the he MMU_WORD_HI & MMU_WORD_LO registers. The returned value is written in the MMU_WORD_LO register. This is a blocking transaction for the processor. |
| 364 | |
| 365 | ==== 3.4.15 MMU_ICACHE_PA_INV & MMU_DCACHE_PA_INV ==== |
| 366 | |
| 367 | Writing any value in the '''MMU_ICACHE_PA_INV''' register (resp. '''MMU_DCACHE_PA_INV''' register) can invalidate a cache line in the instruction cache (resp. data cache). |
| 368 | The values stored in the MMU_WORD_HI & MMU_WORD_LO registers is interpreted as a physical address. |
| 369 | If the instruction cache (resp. data cache) contains a cache line corresponding to this address, it is invalidated. |
| 370 | This is a blocking request for the processor. |
| 371 | |