Changes between Version 41 and Version 42 of VirtualMemory


Ignore:
Timestamp:
Oct 29, 2009, 8:17:30 PM (15 years ago)
Author:
alain
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • VirtualMemory

    v41 v42  
    245245
    246246
    247 === 3.3 generic MMU registers format & mapping ===
     247== 4. generic MMU registers format & mapping ==
    248248
    249249The generic MMU contains a set of 32 bits registers (or pseudo-registers) that can be accessed by operating system,
    … …  
    282282'''Note''': A change to this table should be kept in sync with https://www.soclib.fr/trac/dev/wiki/Component/Iss2Api
    283283
    284 ==== 3.3.1 MMU_PTPR ====
     284=== 4.1 MMU_PTPR ===
    285285
    286286The '''MMU_PTPR''' register contains the base address of the currently used first level page table.
    … …  
    290290|| 00000 || BASE_ADDRESS[39:13] ||
    291291
    292 ==== 3.3.2 MMU_MODE ====
     292=== 4.2 MMU_MODE ===
    293293
    294294The '''MMU_MODE''' register has four bits and these 16 values are described as below.
    … …  
    297297|| (INS TLB) || (DATA TLB) || (INS CACHE) || (DATA CACHE) ||
    298298
    299 ==== 3.3.3 MMU_ICACHE_FLUSH & MMU_DCACHE_FLUSH ====
     299=== 4.3 MMU_ICACHE_FLUSH & MMU_DCACHE_FLUSH ===
    300300
    301301Writing any value  in the '''MMU_ICACHE_FLUSH''' register (resp. '''MMU_DCACHE_FLUSH''' register) invalidates all cache lines stored in the  instruction cache (resp. data cache).
    302302
    303 ==== 3.3.4 MMU_ITLB_INVAL & MMU_DTLB_INVAL ====
     303=== 4.4 MMU_ITLB_INVAL & MMU_DTLB_INVAL ===
    304304
    305305The value written in the 32 bits '''MMU_ITLB_INVAL''' register (resp. '''MMU_DTLB_INVAL''' register) is interpreted as a virtual address. If the instruction TLB (resp. the data TLB) contains an entry corresponding to this address, this entry is invalidated. This is a blocking request for the processor.
    306306
    307 ==== 3.3.5 MMU_ICACHE_INVAL & MMU_DCACHE_INVAL ====
     307=== 4.5 MMU_ICACHE_INVAL & MMU_DCACHE_INVAL ===
    308308
    309309The value written in the 32 bits '''MMU_ICACHE_INVAL''' register (resp. '''MMU_DCACHE_INVAL''' register) is interpreted as a virtual address. This address is translated to a physical address. If the instruction cache (resp. the data cache) contains an entry corresponding to this address, this entry is invalidated. This is a blocking request for the processor.
    310310
    311 ==== 3.3.6 MMU_ICACHE_PREFETCH & MMU_DCACHE_PREFETCH ====
     311=== 4.6 MMU_ICACHE_PREFETCH & MMU_DCACHE_PREFETCH ===
    312312
    313313The value written in the 32 bits '''MMU_ICACHE_PREFETCH''' register (resp. '''MMU_DCACHE_PREFETCH''' register) is interpreted as a virtual address. This address is translated to a physical address. If the instruction cache (resp. the data cache) does not contain the corresponding cache line, this cache line is fetched from memory.
    314314This is a non-blocking request for the processor.
    315315
    316 ==== 3.3.7 MMU_SYNC ====
     316=== 4.7 MMU_SYNC ===
    317317
    318318Writing any value in this '''MMU_SYNC''' register will force execution of posted write requests.
    319319This is a blocking request for the processor.
    320320
    321 ==== 3.3.8 MMU_IETR & MMU_DETR ====
     321=== 4.8 MMU_IETR & MMU_DETR ===
    322322
    323323MMU exceptions are reported in these two registers, as described in section 3.2.
    324324
    325 ==== 3.3.9 MMU_IBVAR & MMU_DBVAR ====
     325=== 4.9 MMU_IBVAR & MMU_DBVAR ===
    326326
    327327Faulty virtual adresses will be written in these two registers.
    328328
    329 ==== 3.3.10 MMU_PARAMS ====
     329=== 4.10 MMU_PARAMS ===
    330330
    331331The '''MMU_PARAMS''' register define the instruction and data caches & TLBs characteristics :
    … …  
    342342 * NBL (4 bits) : Ln(number of bytes per Data or Instruction cache line)
    343343
    344 ==== 3.3.11 MMU_RELEASE ====
     344=== 4.11 MMU_RELEASE ===
    345345
    346346The '''MMU_RELEASE''' register contains the release number for a given hardware implementation :
    … …  
    349349 * IMPLEMENTATION_INDEX (16 bits)
    350350
    351 ==== 3.3.12 MMU_WORD_HI & MMU_WORD_LO ====
    352 
    353 The two 32 bits '''MMU_DOUBLE_HI''' & MMU_DOUBLE_LO''' registers implement a double word data storage.
     351=== 4.12 MMU_WORD_HI & MMU_WORD_LO ===
     352
     353The two 32 bits '''MMU_DOUBLE_HI''' & '''MMU_DOUBLE_LO''' registers implement a double word data storage.
    354354They are used to support cache line invalidation in physical adressing (section 3.3.15), and to support
    355355double words LL & SC accesses (section 3.3.13 & section 3.3.14).
    356356
    357 ==== 3.3.13 MMU_DOUBLE_LL ====
    358 
    359 The value written in the '''MMU_DOUBLE_LL''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Linked Load transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The read value is written in the MMU_WORD_HI & MMU_WORD_LO registers. This is a blocking transaction for the processor.
    360 
    361 ==== 3.4.14 MMU_DOUBLE_SC ====
    362 
    363 The value written in the'''MMU_DOUBLE_SC''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Store Conditionnal transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The transmitted data are the values stored in the he MMU_WORD_HI & MMU_WORD_LO registers. The returned value is written in the MMU_WORD_LO register. This is a blocking transaction for the processor.
    364 
    365 ==== 3.4.15 MMU_ICACHE_PA_INV & MMU_DCACHE_PA_INV ====
     357=== 4.13 MMU_DOUBLE_LL ===
     358
     359The value written in the '''MMU_DOUBLE_LL''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Linked Load transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The read value is written in the MMU_WORD_HI & MMU_WORD_LO registers. This is a blocking request for the processor.
     360
     361=== 4.14 MMU_DOUBLE_SC ===
     362
     363The value written in the'''MMU_DOUBLE_SC''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Store Conditionnal transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The transmitted data are the values stored in the he MMU_WORD_HI & MMU_WORD_LO registers. The returned value is written in the MMU_WORD_LO register. This is a blocking request for the processor.
     364
     365=== 4.15 MMU_ICACHE_PA_INV & MMU_DCACHE_PA_INV ===
    366366
    367367Writing any value in the '''MMU_ICACHE_PA_INV''' register (resp. '''MMU_DCACHE_PA_INV''' register) can invalidate a cache line in the instruction cache (resp. data cache).
    … …  
    369369If the instruction cache (resp. data cache) contains a cache line corresponding to this address, it is invalidated.
    370370This is a blocking request for the processor.
    371