Changes between Version 44 and Version 45 of VirtualMemory

Timestamp:

Apr 30, 2010, 5:41:33 PM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -171 +171 @@
 The possible values for the OperationType field are defined below :
 
-|| Data.OperationType || R X L Z  || semantic    ||
-||                                     ||                      ||
-|| DATA_READ              || 1 0 0 0 || load 32 bits from memory address space ||
-|| DATA_WRITE             || 0 0 0 0 || store 32 bits to memory adress space ||
-|| DATA_LL                    || 1 0 1 0 || load 32 bits from memory address space with reservation ||
-|| DATA_SC                   || 0 0 1 0 || conditionnal store 32 bits to memory address space ||
-|| XTN_READ                 || 1 1 0 0 || load 32 bits from MMU register ||
-|| XTN_WRITE                || 0 1 0 0 || store 32 bits to MMU register ||
-|| DATA_LLRST             || * * * 1 || reset a previous LL reservation ||
-
+|| Data.OperationType     || R X L Z S || semantic                                                ||
+||                                     ||                                                         ||
+|| DATA_READ              || 1 0 0 0 0 || load 32 bits from memory address space                  ||
+|| DATA_WRITE             || 0 0 0 0 0 || store 32 bits to memory adress space                    ||
+|| DATA_LL                || 1 0 1 0 0 || load 32 bits from memory address space with reservation ||
+|| DATA_SC                || 0 0 1 0 0 || conditionnal store 32 bits to memory address space      ||
+|| XTN_READ               || 1 1 0 0 0 || load 32 bits from MMU register                          ||
+|| XTN_WRITE              || 0 1 0 0 0 || store 32 bits to MMU register                           ||
+|| DATA_LLRST             || * * * 1 0 || reset a previous LL reservation                         ||
+|| DATA_SYNC              || * * * * 1 || flush the write buffer before returning                 || 
 Note : Instruction request & data requests are independent :  the processor can issue simultaneous 
 data & instruction requests that have  different execution modes.