282 | | || MMU_ICACHE_PA_INV || 19 || Instruction cache inval physical address || W || |
283 | | || MMU_DCACHE_PA_INV || 20 || Data cache inval physical address || W || |
284 | | || MMU_DOUBLE_LL || 21 || Double word linked load || W || |
285 | | || MMU_DOUBLE_SC || 22 || Double word store conditional || W || |
| 282 | || MMU_ICACHE_PA_INVAL || 19 || Instruction cache inval physical address || W || |
| 283 | || MMU_DCACHE_PA_INVAL || 20 || Data cache inval physical address || W || |
| 284 | || MMU_LL_RESET || 21 || LLSC reservation buffer invalidation || W || |