Changes between Version 54 and Version 55 of VirtualMemory

Timestamp:

Oct 16, 2014, 10:31:02 AM (11 years ago)

Author:

cfuguet

Comment:

Updating MMU registers. Especifically, the physical address extension registers were missing

VirtualMemory

@@ -283 +283 @@
 || MMU_DCACHE_PA_INVAL ||   20   || Data cache inval physical address           || W    || 
 || MMU_LL_RESET        ||   21   || LLSC reservation buffer invalidation        || W    ||
+|| MMU_DOUBLE_LL       ||   22   || 64 bits linked-load transaction             || W    ||
+|| MMU_DOUBLE_SC       ||   23   || 64 bits store-conditional transaction       || W    ||
+|| MMU_DATA_PADDR_EXT  ||   24   || Physical address extension for data access  || W    ||
+|| MMU_INST_PADDR_EXT  ||   25   || Physical address extension for inst access  || W    ||
 
 '''Note''': A change to this table should be synchronised with https://www.soclib.fr/trac/dev/wiki/Component/Iss2Api
@@ -359 +363 @@
 double words LL & SC accesses (section 4.13 & section 4.14).
 
-=== 4.13 MMU_DOUBLE_LL ===
-
-The value written in the '''MMU_DOUBLE_LL''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Linked Load transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The read value is written in the MMU_WORD_HI & MMU_WORD_LO registers. This is a blocking request for the processor.
-
-=== 4.14 MMU_DOUBLE_SC ===
-
-The value written in the'''MMU_DOUBLE_SC''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Store Conditionnal transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The transmitted data are the values stored in the he MMU_WORD_HI & MMU_WORD_LO registers. The returned value is written in the MMU_WORD_LO register. This is a blocking request for the processor. 
-
-=== 4.15 MMU_ICACHE_PA_INV & MMU_DCACHE_PA_INV ===
+
+=== 4.13 MMU_ICACHE_PA_INV & MMU_DCACHE_PA_INV ===
 
 Writing any value in the '''MMU_ICACHE_PA_INV''' register (resp. '''MMU_DCACHE_PA_INV''' register) can invalidate a cache line in the instruction cache (resp. data cache).
@@ -373 +370 @@
 If the instruction cache (resp. data cache) contains a cache line corresponding to this address, it is invalidated.
 This is a blocking request for the processor.
+
+=== 4.14 MMU_DOUBLE_LL ===
+
+The value written in the '''MMU_DOUBLE_LL''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Linked Load transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The read value is written in the MMU_WORD_HI & MMU_WORD_LO registers. This is a blocking request for the processor.
+
+=== 4.15 MMU_DOUBLE_SC ===
+
+The value written in the'''MMU_DOUBLE_SC''' register is interpreted as a virtual address. It is translated to a physical address, and a double word (64 bits) Store Conditionnal transaction is initiated. The access must be aligned on a double word boundary (the 3 LSB bits of the address are ignored). The transmitted data are the values stored in the he MMU_WORD_HI & MMU_WORD_LO registers. The returned value is written in the MMU_WORD_LO register. This is a blocking request for the processor.
+
+=== 4.16 MMU_DATA_PADDR_EXT ===
+
+The value written in the '''MMU_DATA_PADDR_EXT''' register is used as a physical address extension during a data access. It is only used when the DTLB is deactivated. It is used to access a memory location which is beyond the 4 Gbytes address space.
+
+=== 4.17 MMU_INST_PADDR_EXT ===
+
+The value written in the '''MMU_INST_PADDR_EXT''' register is used as a physical address extension during an instruction access. It is only used when the ITLB is deactivated. It is used to access a memory location which is beyond the 4 Gbytes address space.
+