Changes between Version 61 and Version 62 of VirtualMemory
- Timestamp:
- Jun 9, 2019, 1:19:48 PM (6 years ago)
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VirtualMemory
v61 v62 45 45 46 46 * PTD1 47 ||V||T|| reserved (2 bits) || P TBA(28 bits) ||47 ||V||T|| reserved (2 bits) || PPN2 (28 bits) || 48 48 49 49 The various fields are defined as follows : … … 59 59 || G || Global bit || Entry not invalidated in TLB flush when 1 (set by the OS) || 60 60 || D || Dirty bit || The page has been modified when 1 (set by the hardware) || 61 || PPN1 || Physical Page Number || Concatened to the page offset to build the physical address||62 || P TBA || Page Table Base Address || Second level page table base address / 4096||61 || PPN1 || Physical Page Number in PTE1 || PPN of a the First Level page || 62 || PPN2 || Physical Page Number in PTE2 || PPN of the Second level page table || 63 63 64 64 The L, R, D bits are used by the operating system to implement the page replacement policy. … … 70 70 If the entry is a PTE1, the PPN1 value (19 bits) must be concatened with the page offset (21 bits) to build the 40 bits physical address. 71 71 72 If the entry is a PTD1, the P TBAvalue (28 bits) must be left-shifted by 12 bits to define the base address of the level 2 page table. The page table being aligned in memory, the 12 LSB bits of this base address have a 0 value.72 If the entry is a PTD1, the PPN2 value (28 bits) must be left-shifted by 12 bits to define the base address of the level 2 page table. The page table being aligned in memory, the 12 LSB bits of this base address have a 0 value. 73 73 74 74 The ''reserved'' bits are are specified for future hardware extensions, and must not be used by the operating system.
