Changes between Version 7 and Version 8 of VirtualMemory

Timestamp:

Jun 28, 2009, 10:43:21 AM (15 years ago)

Author:

alain

Comment:

--

VirtualMemory

@@ -13 +13 @@
 == 1. Page Table Organisation ==
 
-The TSAR virtual memory uses a paginated approach. The TSAR architecture defines two page sizes :
--       4 Kbytes pages
--       2 Mbytes pages
+The TSAR architecture defines two page sizes : 4 Kbytes pages, and 2 Mbytes pages.
 The virtual address space size is 4 Gbytes (32 bits virtual addresses). 
 The physical address space is limited to 1 Tbytes (40 bits physical addresses). 
-
-The page table are build by the operating system, and are stored in memory. They are used for both the VPN (Virtual Page number)  to PPN (Physical Page Number) translation, and for access rights checking.
+The page table are build by the operating system, and are stored in the main memory. 
 
 === 1.1 Two levels Page Table structure ===
@@ -25 +22 @@
 As described below, the Page Table has a hierarchical two levels structure : 
 
+[[Image(two.png, nolink)]]
 
-
-The general mapping constraints are the following
--       All page tables (first & second level) must be aligned : the page table base adress must be a multiple of 8K bytes for a first level page table, and multiple of 4K bytes for a second level page table.
--       The page tables can be placed anywhere in the physical address space.
--       The PTPR register (located in the generic MMU, and initialised by  the OS at each context switch) contains actually the 27 MSB bits  of the first level page table base address. In case of TLB MISS, it is extended (left-shifted) to 40 bits by the hardware.
+ * All page tables (first & second level) must be aligned : the page table base adress must be a multiple of 8K bytes for a first level page table, and multiple of 4K bytes for a second level page table.
+ * The page tables can be placed anywhere in the physical address space.
+ * The PTPR register is located in the generic MMU, and is re-initialised by  the OS at each context switch. It contains the 27 MSB bits  of the first level page table base address, and is extended (left-shifted) to 40 bits by the Table-Walk FSM in case of TLB MISS.
 
 === 1.2 First Level Page Table Entry Format ===