| [46] | 1 | % This file was created with JabRef 2.5. |
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| 3 | |
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| 4 | @INPROCEEDINGS{Cabodi09Speeding, |
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| 5 | author = {G. Cabodi and P. Camurati and L. Garcia and M. Murciano and S. Nocco |
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| 6 | and S. Quer}, |
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| 7 | title = {Speeding up Model Checking by Exploiting Explicit and Hidden Verification |
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| 8 | Constraints}, |
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| 9 | booktitle = {DATE '09: Proceedings of the conference on Design, Automation and |
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| 10 | Test in Europe}, |
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| 11 | year = {2009}, |
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| 12 | pages = {1686-1691}, |
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| 13 | abstract = {Constraints represent a key component of state- |
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| 14 | |
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| 15 | of-the-art verification tools based on compositional approaches |
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| 16 | |
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| 17 | and assumeâguarantee reasoning. In recent years, most of the |
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| 18 | |
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| 19 | research efforts on verification constraints have focused on |
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| 20 | |
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| 21 | defining formats and techniques to encode, or to synthesize, |
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| 22 | |
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| 23 | constraints starting from the specification of the design. |
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| 24 | |
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| 25 | In this paper, we analyze the impact of constraints on the |
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| 26 | |
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| 27 | performance of model checking tools, and we discuss how to |
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| 28 | |
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| 29 | effectively exploit them. We also introduce an approach to |
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| 30 | |
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| 31 | explicitly derive verification constraints hidden in the design |
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| 32 | |
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| 33 | and/or in the property under verification. Such constraints may |
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| 34 | |
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| 35 | simply come from true design constraints, embedded within the |
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| 36 | |
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| 37 | properties, or may be generated in the general effort to reduce or |
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| 38 | |
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| 39 | partition the state space. Experimental results show that, in both |
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| 40 | |
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| 41 | cases, we can reap benefits for the overall verification process |
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| 42 | |
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| 43 | in several hard-to-solve designs, where we obtain speed-ups of |
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| 44 | |
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| 45 | more than one order of magnitude.}, |
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| 46 | file = {:Composition/Speeding up MC by exploiting Explicit09.PDF:PDF}, |
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| 47 | owner = {cecile}, |
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| 48 | timestamp = {2009.04.30} |
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| 49 | } |
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| 50 | |
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| 51 | @INPROCEEDINGS{6128043, |
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| 52 | author = {Yuzhang Feng and Veeramani, A. and Kanagasabai, R. and Seungmin Rho}, |
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| 53 | title = {Automatic Service Composition via Model Checking}, |
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| 54 | booktitle = {Services Computing Conference (APSCC), 2011 IEEE Asia-Pacific}, |
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| 55 | year = {2011}, |
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| 56 | pages = {477 -482}, |
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| 57 | month = {dec.}, |
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| 58 | abstract = {Web service composition is the process of constructing a set of Web |
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| 59 | services which, when invoked with some user input in a particular |
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| 60 | order, can produce the output to the user's requirements. This paper |
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| 61 | proposes a novel model checking based approach for automated service |
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| 62 | composition. Modeling services as a set of interleaved processes |
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| 63 | in a class of process algebra, we formulate service composition as |
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| 64 | model checking asserted on a specific type of property on the model. |
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| 65 | We show that, under this formulation, correct composition workflows |
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| 66 | can be constructed from the counter-examples provided by model checking. |
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| 67 | With a case study on online hotel booking services, we demonstrate |
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| 68 | that the proposed approach can support directed a cyclic composition |
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| 69 | graphs and the generated composition graphs are automatically verified.}, |
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| 70 | doi = {10.1109/APSCC.2011.54}, |
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| 71 | file = {:/users/outil/verif/biblio/Composition/AutomaticServiceCompositionViaModelChecking2011.pdf:PDF}, |
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| 72 | keywords = {Web service composition;automated service composition;directed acyclic |
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| 73 | composition graph;interleaved process;model checking;online hotel |
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| 74 | booking services;process algebra;user requirements;Web services;directed |
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| 75 | graphs;formal verification;hotel industry;process algebra;} |
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| 76 | } |
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| 77 | |
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| 78 | @INCOLLECTION{springerlink:10.1007/978-3-642-16901-4_15, |
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| 79 | author = {Lomuscio, Alessio and Strulo, Ben and Walker, Nigel and Wu, Peng}, |
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| 80 | title = {Assume-Guarantee Reasoning with Local Specifications}, |
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| 81 | booktitle = {Formal Methods and Software Engineering}, |
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| 82 | publisher = {Springer Berlin / Heidelberg}, |
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| 83 | year = {2010}, |
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| 84 | editor = {Dong, Jin and Zhu, Huibiao}, |
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| 85 | volume = {6447}, |
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| 86 | series = {Lecture Notes in Computer Science}, |
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| 87 | pages = {204-219}, |
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| 88 | note = {10.1007/978-3-642-16901-4_15}, |
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| 89 | abstract = {We investigate assume-guarantee reasoning for global specifications |
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| 90 | consisting of conjunctions of local specifications. We present a |
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| 91 | sound and complete assume-guarantee rule that permits reasoning about |
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| 92 | individual modules for local specifications and draws conclusions |
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| 93 | on global specifications. We illustrate our approach with an example |
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| 94 | from the field of network congestion control, where different agents |
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| 95 | are responsible for controlling packet flow across a shared infrastructure. |
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| 96 | In this context, we derive an assume-guarantee rule for system stability, |
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| 97 | and show that this rule is valuable to reason about any number of |
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| 98 | agents, any initial flow configuration, and any topology of bounded |
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| 99 | degree.}, |
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| 100 | affiliation = {Department of Computing, Imperial College London, UK}, |
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| 101 | file = {:/users/outil/verif/biblio/Composition/AGRwithLocalSpecification2010.pdf:PDF}, |
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| 102 | isbn = {978-3-642-16900-7}, |
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| 103 | keyword = {Computer Science}, |
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| 104 | keywords = {Compositional reasoning}, |
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| 105 | url = {http://dx.doi.org/10.1007/978-3-642-16901-4_15} |
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| 106 | } |
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| 107 | |
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| 108 | @INPROCEEDINGS{Tripakis201, |
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| 109 | author = {Tripakis, Stavros and Andrade, Hugo and Ghosal, Arkadeb and Limaye, |
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| 110 | Rhishikesh and Ravindran, Kaushik and Wang, Guoqiang and Yang, Guang |
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| 111 | and Kormerup, Jacob and Wong, Ian}, |
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| 112 | title = {Correct and non-defensive glue design using abstract models}, |
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| 113 | booktitle = {Proceedings of the seventh IEEE/ACM/IFIP international conference |
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| 114 | on Hardware/software codesign and system synthesis}, |
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| 115 | year = {2011}, |
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| 116 | series = {CODES+ISSS '11}, |
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| 117 | pages = {59--68}, |
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| 118 | address = {New York, NY, USA}, |
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| 119 | publisher = {ACM}, |
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| 120 | abstract = { Current hardware design practice often relies on integration of components, |
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| 121 | some of which may be IP or legacy blocks. While integration eases |
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| 122 | design by allowing modularization and component reuse, it is still |
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| 123 | done in a mostly ad hoc manner. Designers work with descriptions |
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| 124 | of components that are either informal or incomplete (e.g., documents |
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| 125 | in English, structural but non-behavioral specifications in IP-XACT) |
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| 126 | or too low-level (e.g., HDL code), and have little to no automatic |
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| 127 | support for stitching the components together. Providing such support |
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| 128 | is the glue design problem. |
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| 129 | |
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| 130 | This paper addresses this problem using a model-based approach. The |
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| 131 | key idea is to use high-level models, such as dataflow graphs, that |
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| 132 | enable efficient automated analysis. The analysis can be used to |
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| 133 | derive performance properties of the system (e.g., component compatibility, |
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| 134 | throughput, etc.), optimize resource usage (e.g., buffer sizes), |
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| 135 | and even synthesize low-level code (e.g., control logic). However, |
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| 136 | these models are only abstractions of the real system, and often |
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| 137 | omit critical information. As a result, the analysis outcomes may |
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| 138 | be defensive (e.g., buffers that are too big) or even incorrect (e.g., |
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| 139 | buffers that are too small). The paper examines these situations |
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| 140 | and proposes a correct and non-defensive design methodology that |
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| 141 | employs the right models to explore accurate performance and resource |
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| 142 | trade-offs. }, |
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| 143 | acmid = {2039382}, |
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| 144 | doi = {http://doi.acm.org/10.1145/2039370.2039382}, |
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| 145 | isbn = {978-1-4503-0715-4}, |
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| 146 | keywords = {abstraction, data flow, glue design, non-defensiveness}, |
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| 147 | location = {Taipei, Taiwan}, |
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| 148 | numpages = {10}, |
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| 149 | url = {http://doi.acm.org/10.1145/2039370.2039382} |
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| 150 | } |
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| 151 | |
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| 152 | @ARTICLE{5374376, |
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| 153 | author = {Hao Zheng and Haiqiong Yao and Yoneda, T.}, |
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| 154 | title = {Modular Model Checking of Large Asynchronous Designs with Efficient |
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| 155 | Abstraction Refinement}, |
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| 156 | journal = {Computers, IEEE Transactions on}, |
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| 157 | year = {2010}, |
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| 158 | volume = {59}, |
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| 159 | pages = {561 -573}, |
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| 160 | number = {4}, |
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| 161 | month = {april }, |
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| 162 | abstract = {Divide-and-conquer is essential to address state explosion in model |
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| 163 | checking. Verifying each individual component in a system, in isolation, |
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| 164 | efficiently requires an appropriate context, which traditionally |
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| 165 | is obtained by hand. This paper presents an efficient modular model |
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| 166 | checking approach for asynchronous design verification. It is equipped |
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| 167 | with a novel abstraction refinement method that can refine a component |
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| 168 | abstraction to be accurate enough for successful verification. It |
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| 169 | is fully automated, and eliminates the need of finding an accurate |
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| 170 | context when verifying each individual component, although such a |
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| 171 | context is still highly desirable. This method is also enhanced with |
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| 172 | additional state space reduction techniques. The experiments on several |
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| 173 | nontrivial asynchronous designs show that this method efficiently |
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| 174 | removes impossible behaviors from each component including ones violating |
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| 175 | correctness requirements.}, |
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| 176 | doi = {10.1109/TC.2009.187}, |
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| 177 | file = {:/users/outil/verif/biblio/Composition/ModularMCLargeAsynchronousDesignwithAR2010.pdf:PDF}, |
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| 178 | issn = {0018-9340}, |
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| 179 | keywords = {abstraction refinement;abstraction refinement method;large asynchronous |
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| 180 | designs;modular model checking;state explosion;state space reduction |
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| 181 | techniques;formal verification;state-space methods;} |
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| 182 | } |
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| 183 | |
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