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huff_synchro.sim @ 105

Last change on this file since 105 was 105, checked in by cecile, 12 years ago
Hufmann case study
File size: 1.4 KB

Line
1	.inputs addr<0> addr<1> addr<2> addr<3> addr<4>
2	.latches character<0> character<1> character<2> character<3> character<4> character<5> character<6> character<7> decoder.state<0> decoder.state<1> decoder.state<2> decoder.state<3> decoder.state<4> decoder.state<5> decoder.state<6> decoder.state<7> decoder.state<8> decoder.state<9> encoder.shiftreg<0> encoder.shiftreg<1> encoder.shiftreg<2> encoder.shiftreg<3> encoder.shiftreg<4> encoder.shiftreg<5> encoder.shiftreg<6> encoder.shiftreg<7> encoder.shiftreg<8> encoder.shiftreg<9> start
3	.outputs plain<0> plain<1> plain<2> plain<3> plain<4> plain<5> plain<6> plain<7>
4	.initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5
6	.start_vectors
7
8	# addr<0> addr<1> addr<2> addr<3> addr<4> ; character<0> character<1> character<2> character<3> character<4> character<5> character<6> character<7> decoder.state<0> decoder.state<1> decoder.state<2> decoder.state<3> decoder.state<4> decoder.state<5> decoder.state<6> decoder.state<7> decoder.state<8> decoder.state<9> encoder.shiftreg<0> encoder.shiftreg<1> encoder.shiftreg<2> encoder.shiftreg<3> encoder.shiftreg<4> encoder.shiftreg<5> encoder.shiftreg<6> encoder.shiftreg<7> encoder.shiftreg<8> encoder.shiftreg<9> start ; plain<0> plain<1> plain<2> plain<3> plain<4> plain<5> plain<6> plain<7>
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10	0 0 0 0 0 ;
11	0 0 0 0 0 ;
12	0 0 0 0 0 ;
13	0 0 0 0 0 ;
14	0 0 1 0 0 ;
15	0 0 1 0 0 ;
16	0 0 1 0 0 ;
17	0 0 1 0 0 ;
18	0 0 1 0 0 ;
19	0 0 0 0 0 ;
20	0 0 0 0 0 ;
21	0 0 0 0 0 ;
22	0 0 0 0 0 ;
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