module environment(clk,val,addr,ack);
  input clk;
  output [4:0] addr;
  output val;
  reg val;
  input ack;

  reg addr;
  initial addr = 0;
  initial  val = 1;
  always @(posedge clk) begin
    val = 0;
    if(ack == 1)
    begin
      val = 1;
      case(addr)
        0 : addr = 4;
        4 : addr = 0; 
        default : 
            addr = 0;
     endcase
    end
  end
  

endmodule