module environment(clk,val,i_addr,i_val,addr,ack);
  input clk;
  input i_val;
  input [4:0]i_addr;
  output [4:0] addr;
  output val;
  reg val;
  reg r_val;
  input ack;

  reg addr;
  initial addr = 0;
  initial  val = 1;
  initial  r_val = 1;
  always @(posedge clk) begin
    val = 0;
    if(ack == 1)
    begin
      val = (r_val == 1)?0:i_val;
      addr = i_addr;
    end
    r_val = i_val;
  end
  

endmodule