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1 | typedef enum {S0, S1, S2, S3} MState; |
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2 | |
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3 | module machine_concret (clk, i1, o1, o2, r_i1); |
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4 | |
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5 | input clk; |
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6 | input i1; |
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7 | output o1; |
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8 | output o2; |
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9 | output r_i1; |
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10 | |
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11 | MState reg m_state; |
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12 | reg o1; |
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13 | reg o2; |
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14 | reg r_i1; |
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15 | |
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16 | initial |
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17 | begin |
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18 | m_state = S0; |
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19 | o1 = 0; |
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20 | o2 = 0; |
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21 | r_i1 = i1; |
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22 | end |
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23 | |
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24 | always @ (posedge clk) begin |
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25 | |
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26 | r_i1 = i1; |
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27 | case (m_state) |
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28 | S0: |
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29 | if (i1==1) |
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30 | begin |
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31 | m_state = S1; |
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32 | o1 = 1; |
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33 | o2 = 0; |
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34 | end |
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35 | else |
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36 | begin |
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37 | o1 = 0; |
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38 | o2 = 0; |
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39 | m_state = S0; |
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40 | end |
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41 | |
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42 | S1: |
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43 | begin |
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44 | m_state = S2; |
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45 | o1 = 0; |
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46 | o2 = 1; |
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47 | end |
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48 | |
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49 | S2: |
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50 | begin |
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51 | m_state = S3; |
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52 | o1 = 1; |
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53 | o2 = 1; |
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54 | end |
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55 | |
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56 | S3: |
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57 | begin |
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58 | o1 = 1; |
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59 | o2 = 1; |
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60 | m_state = S3; |
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61 | end |
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62 | |
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63 | endcase |
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64 | |
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65 | end |
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66 | |
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67 | endmodule |
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