typedef enum{machine_concret1_Abs1_STATE_28,machine_concret1_Abs1_STATE_31,machine_concret1_Abs1_STATE_30,machine_concret1_Abs1_STATE_32,machine_concret1_Abs1_STATE_27,machine_concret1_Abs1_STATE_29,machine_concret1_Abs1_STATE_35,machine_concret1_Abs1_STATE_39,machine_concret1_Abs1_STATE_41,machine_concret1_Abs1_STATE_42,machine_concret1_Abs1_STATE_34,machine_concret1_Abs1_STATE_44,machine_concret1_Abs1_STATE_38,machine_concret1_Abs1_STATE_40,machine_concret1_Abs1_STATE_36,machine_concret1_Abs1_STATE_33,machine_concret1_Abs1_STATE_45,machine_concret1_Abs1_STATE_43,machine_concret1_Abs1_STATE_46,machine_concret1_Abs1_STATE_37} machine_concret1_Abs1_STATE; module machine_concret1_Abs1(clk,i1,o1,o2,r_i1); input clk; input i1; output r_i1; output o1; output o2; reg r_i1; reg o1; reg o2; machine_concret1_Abs1_STATE reg state; wire nd_r_i1; wire nd_o1; wire nd_o2; wire nd_aff0; wire nd_aff1; assign nd_r_i1 = $ND(0,1); assign nd_o1 = $ND(0,1); assign nd_o2 = $ND(0,1); assign nd_aff0 = $ND(0,1); assign nd_aff1 = $ND(0,1); initial begin state = $ND(machine_concret1_Abs1_STATE_27,machine_concret1_Abs1_STATE_29,machine_concret1_Abs1_STATE_33,machine_concret1_Abs1_STATE_37); if(state == machine_concret1_Abs1_STATE_27) begin r_i1 = 0; o1 = 0; o2 = 0; end else begin if(state == machine_concret1_Abs1_STATE_29) begin r_i1 = 0; o1 = 0; o2 = 0; end else begin if(state == machine_concret1_Abs1_STATE_33) begin r_i1 = 0; o1 = 0; o2 = 0; end else begin o1 = 0; o2 = 0; r_i1 = nd_r_i1; end end end end always @(posedge clk) begin case(state) machine_concret1_Abs1_STATE_28: begin state = machine_concret1_Abs1_STATE_28; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end machine_concret1_Abs1_STATE_31: begin state = machine_concret1_Abs1_STATE_31; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end machine_concret1_Abs1_STATE_30: begin state = machine_concret1_Abs1_STATE_31; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end machine_concret1_Abs1_STATE_32: begin if(nd_aff0 == 1) begin state = machine_concret1_Abs1_STATE_30; o2 = 1; r_i1 = nd_r_i1; o1 = nd_o1; end else begin state = machine_concret1_Abs1_STATE_32; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end end machine_concret1_Abs1_STATE_27: begin state = machine_concret1_Abs1_STATE_28; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end machine_concret1_Abs1_STATE_29: begin if(nd_aff0 == 1) begin state = machine_concret1_Abs1_STATE_30; o2 = 1; r_i1 = nd_r_i1; o1 = nd_o1; end else begin state = machine_concret1_Abs1_STATE_32; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end end machine_concret1_Abs1_STATE_35: begin state = machine_concret1_Abs1_STATE_35; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end machine_concret1_Abs1_STATE_39: begin state = machine_concret1_Abs1_STATE_39; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end machine_concret1_Abs1_STATE_41: begin state = machine_concret1_Abs1_STATE_39; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end machine_concret1_Abs1_STATE_42: begin if(nd_aff0 == 1) begin state = machine_concret1_Abs1_STATE_41; o2 = 1; r_i1 = nd_r_i1; o1 = nd_o1; end else begin state = machine_concret1_Abs1_STATE_42; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end end machine_concret1_Abs1_STATE_34: begin state = machine_concret1_Abs1_STATE_35; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end machine_concret1_Abs1_STATE_44: begin state = machine_concret1_Abs1_STATE_39; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end machine_concret1_Abs1_STATE_38: begin state = machine_concret1_Abs1_STATE_39; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end machine_concret1_Abs1_STATE_40: begin if(nd_aff0 == 1) begin state = machine_concret1_Abs1_STATE_41; o2 = 1; r_i1 = nd_r_i1; o1 = nd_o1; end else begin state = machine_concret1_Abs1_STATE_42; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end end machine_concret1_Abs1_STATE_36: begin if(nd_aff0 == 1) begin state = machine_concret1_Abs1_STATE_34; o1 = 1; r_i1 = nd_r_i1; o2 = nd_o2; end else begin state = machine_concret1_Abs1_STATE_36; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end end machine_concret1_Abs1_STATE_33: begin if(nd_aff0 == 1) begin state = machine_concret1_Abs1_STATE_34; o1 = 1; r_i1 = nd_r_i1; o2 = nd_o2; end else begin state = machine_concret1_Abs1_STATE_36; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end end machine_concret1_Abs1_STATE_45: begin if(nd_aff0 == 1) begin state = machine_concret1_Abs1_STATE_44; o1 = 1; r_i1 = nd_r_i1; o2 = nd_o2; end else begin state = machine_concret1_Abs1_STATE_45; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end end machine_concret1_Abs1_STATE_43: begin if(nd_aff0 == 1) begin state = machine_concret1_Abs1_STATE_44; o1 = 1; r_i1 = nd_r_i1; o2 = nd_o2; end else begin state = machine_concret1_Abs1_STATE_45; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end end machine_concret1_Abs1_STATE_46: begin if(nd_aff0 == 1) begin if(nd_aff1 == 1) begin state = machine_concret1_Abs1_STATE_38; o1 = 1; o2 = 1; r_i1 = nd_r_i1; end else begin state = machine_concret1_Abs1_STATE_40; o1 = 1; r_i1 = nd_r_i1; o2 = nd_o2; end end else begin if(nd_aff1 == 1) begin state = machine_concret1_Abs1_STATE_43; o2 = 1; r_i1 = nd_r_i1; o1 = nd_o1; end else begin state = machine_concret1_Abs1_STATE_46; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end end end machine_concret1_Abs1_STATE_37: begin if(nd_aff0 == 1) begin if(nd_aff1 == 1) begin state = machine_concret1_Abs1_STATE_38; o1 = 1; o2 = 1; r_i1 = nd_r_i1; end else begin state = machine_concret1_Abs1_STATE_40; o1 = 1; r_i1 = nd_r_i1; o2 = nd_o2; end end else begin if(nd_aff1 == 1) begin state = machine_concret1_Abs1_STATE_43; o2 = 1; r_i1 = nd_r_i1; o1 = nd_o1; end else begin state = machine_concret1_Abs1_STATE_46; r_i1 = nd_r_i1; o1 = nd_o1; o2 = nd_o2; end end end endcase end endmodule