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[4] | 1 | /* ----- Symbolic variables ----- */ |
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| 2 | typedef enum {S0, S1, S2, S3} MState; |
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| 3 | |
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| 4 | /* ----- Main Module ----- */ |
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| 5 | module machine_concret (clk, i1, o1, o2, r_i1); |
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| 6 | |
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| 7 | input clk; |
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| 8 | input i1; |
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| 9 | output o1; |
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| 10 | output o2; |
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| 11 | output r_i1; |
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| 12 | |
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| 13 | MState reg m_state; |
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| 14 | reg o1, o2; |
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| 15 | reg r_i1; |
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| 16 | |
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| 17 | initial |
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| 18 | begin |
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| 19 | m_state = S0; |
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| 20 | o1 = 0; |
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| 21 | o2 = 0; |
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| 22 | r_i1 = i1; |
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| 23 | end //initial |
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| 24 | |
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| 25 | always @ (posedge clk) begin |
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| 26 | |
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| 27 | r_i1 = i1; |
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| 28 | case (m_state) |
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| 29 | S0: |
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| 30 | if (i1==1) |
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| 31 | begin |
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| 32 | m_state = S1; |
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| 33 | o1 = 1; |
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| 34 | o2 = 0; |
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| 35 | end |
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| 36 | else |
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| 37 | begin |
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| 38 | o1 = 0; |
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| 39 | o2 = 0; |
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| 40 | m_state = S0; |
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| 41 | end |
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| 42 | |
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| 43 | S1: |
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| 44 | begin |
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| 45 | m_state = S2; |
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| 46 | o1 = 0; |
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| 47 | o2 = 1; |
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| 48 | end |
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| 49 | |
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| 50 | S2: |
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| 51 | begin |
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| 52 | m_state = S3; |
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| 53 | o1 = 1; |
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| 54 | o2 = 1; |
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| 55 | end |
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| 56 | |
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| 57 | S3: |
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| 58 | begin |
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| 59 | o1 = 1; |
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| 60 | o2 = 1; |
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| 61 | m_state = S3; |
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| 62 | end |
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| 63 | |
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| 64 | endcase |
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| 65 | // r_i1 = i1; |
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| 66 | |
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| 67 | end //always |
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| 68 | |
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| 69 | endmodule |
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