Line | |
---|
1 | /* ----- Symbolic variables ----- */ |
---|
2 | typedef enum {S0, S1, S2, S3} MState; |
---|
3 | |
---|
4 | /* ----- Main Module ----- */ |
---|
5 | module machine_concret (clk, i1, o1, o2, r_i1); |
---|
6 | |
---|
7 | input clk; |
---|
8 | input i1; |
---|
9 | output o1; |
---|
10 | output o2; |
---|
11 | output r_i1; |
---|
12 | |
---|
13 | MState reg m_state; |
---|
14 | reg o1, o2; |
---|
15 | reg r_i1; |
---|
16 | |
---|
17 | initial |
---|
18 | begin |
---|
19 | m_state = S0; |
---|
20 | o1 = 0; |
---|
21 | o2 = 0; |
---|
22 | r_i1 = i1; |
---|
23 | end //initial |
---|
24 | |
---|
25 | always @ (posedge clk) begin |
---|
26 | |
---|
27 | r_i1 = i1; |
---|
28 | case (m_state) |
---|
29 | S0: |
---|
30 | if (i1==1) |
---|
31 | begin |
---|
32 | m_state = S1; |
---|
33 | o1 = 1; |
---|
34 | o2 = 0; |
---|
35 | end |
---|
36 | else |
---|
37 | begin |
---|
38 | o1 = 0; |
---|
39 | o2 = 0; |
---|
40 | m_state = S0; |
---|
41 | end |
---|
42 | |
---|
43 | S1: |
---|
44 | begin |
---|
45 | m_state = S2; |
---|
46 | o1 = 0; |
---|
47 | o2 = 1; |
---|
48 | end |
---|
49 | |
---|
50 | S2: |
---|
51 | begin |
---|
52 | m_state = S3; |
---|
53 | o1 = 1; |
---|
54 | o2 = 1; |
---|
55 | end |
---|
56 | |
---|
57 | S3: |
---|
58 | begin |
---|
59 | o1 = 1; |
---|
60 | o2 = 1; |
---|
61 | m_state = S3; |
---|
62 | end |
---|
63 | |
---|
64 | endcase |
---|
65 | // r_i1 = i1; |
---|
66 | |
---|
67 | end //always |
---|
68 | |
---|
69 | endmodule |
---|
Note: See
TracBrowser
for help on using the repository browser.