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| 57 | |
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| 58 | <H2><A NAME="SECTION00070000000000000000"> |
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| 59 | Bibliography</A> |
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| 60 | </H2><DL COMPACT><DD><P></P><DT><A NAME="Bahar93">1</A> |
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| 61 | <DD> |
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| 62 | R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, and |
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| 63 | F. Somenzi. |
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| 64 | <BR>Algebraic decision diagrams and their applications. |
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| 65 | <BR>In <EM>Proceedings of the International Conference on Computer-Aided |
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| 66 | Design</EM>, pages 188-191, Santa Clara, CA, November 1993. |
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| 67 | |
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| 68 | <P></P><DT><A NAME="Bollig95">2</A> |
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| 69 | <DD> |
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| 70 | B. Bollig, M. Löbbing, and I. Wegener. |
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| 71 | <BR>Simulated annealing to improve variable orderings for OBDDs. |
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| 72 | <BR>Presented at the International Workshop on Logic Synthesis, |
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| 73 | Granlibakken, CA, May 1995. |
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| 74 | |
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| 75 | <P></P><DT><A NAME="BBR">3</A> |
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| 76 | <DD> |
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| 77 | K. S. Brace, R. L. Rudell, and R. E. Bryant. |
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| 78 | <BR>Efficient implementation of a BDD package. |
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| 79 | <BR>In <EM>Proceedings of the 27th Design Automation Conference</EM>, pages |
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| 80 | 40-45, Orlando, FL, June 1990. |
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| 81 | |
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| 82 | <P></P><DT><A NAME="VIS">4</A> |
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| 83 | <DD> |
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| 84 | R. K. Brayton et al. |
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| 85 | <BR>VIS: A system for verification and synthesis. |
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| 86 | <BR>Technical Report UCB/ERL M95/104, Electronics Research Lab, Univ. of |
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| 87 | California, December 1995. |
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| 88 | |
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| 89 | <P></P><DT><A NAME="BDD">5</A> |
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| 90 | <DD> |
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| 91 | R. E. Bryant. |
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| 92 | <BR>Graph-based algorithms for Boolean function manipulation. |
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| 93 | <BR><EM>IEEE Transactions on Computers</EM>, C-35(8):677-691, August 1986. |
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| 94 | |
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| 95 | <P></P><DT><A NAME="Drechs95">6</A> |
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| 96 | <DD> |
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| 97 | R. Drechsler, B. Becker, and N. Göckel. |
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| 98 | <BR>A genetic algorithm for variable ordering of OBDDs. |
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| 99 | <BR>Presented at the International Workshop on Logic Synthesis, |
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| 100 | Granlibakken, CA, May 1995. |
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| 101 | |
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| 102 | <P></P><DT><A NAME="Friedman90">7</A> |
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| 103 | <DD> |
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| 104 | S. J. Friedman and K. J. Supowit. |
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| 105 | <BR>Finding the optimal variable ordering for binary decision diagrams. |
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| 106 | <BR><EM>IEEE Transactions on Computers</EM>, 39(5):710-713, May 1990. |
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| 107 | |
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| 108 | <P></P><DT><A NAME="Fujita91b">8</A> |
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| 109 | <DD> |
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| 110 | M. Fujita, Y. Matsunaga, and T. Kakuda. |
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| 111 | <BR>On variable ordering of binary decision diagrams for the application |
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| 112 | of multi-level logic synthesis. |
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| 113 | <BR>In <EM>Proceedings of the European Conference on Design Automation</EM>, |
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| 114 | pages 50-54, Amsterdam, February 1991. |
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| 115 | |
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| 116 | <P></P><DT><A NAME="Held62">9</A> |
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| 117 | <DD> |
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| 118 | M. Held and R. M. Karp. |
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| 119 | <BR>A dynamic programming approach to sequencing problems. |
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| 120 | <BR><EM>J. SIAM</EM>, 10(1):196-210, 1962. |
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| 121 | |
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| 122 | <P></P><DT><A NAME="Ishiur91">10</A> |
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| 123 | <DD> |
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| 124 | N. Ishiura, H. Sawada, and S. Yajima. |
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| 125 | <BR>Minimization of binary decision diagrams based on exchanges of |
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| 126 | variables. |
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| 127 | <BR>In <EM>Proceedings of the International Conference on Computer-Aided |
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| 128 | Design</EM>, pages 472-475, Santa Clara, CA, November 1991. |
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| 129 | |
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| 130 | <P></P><DT><A NAME="Jeong93">11</A> |
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| 131 | <DD> |
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| 132 | S.-W. Jeong, T.-S. Kim, and F. Somenzi. |
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| 133 | <BR>An efficient method for optimal BDD ordering computation. |
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| 134 | <BR>In <EM>International Conference on VLSI and CAD (ICVC'93)</EM>, Taejon, |
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| 135 | Korea, November 1993. |
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| 136 | |
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| 137 | <P></P><DT><A NAME="Minato93">12</A> |
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| 138 | <DD> |
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| 139 | S.-I. Minato. |
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| 140 | <BR>Zero-suppressed BDDs for set manipulation in combinatorial |
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| 141 | problems. |
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| 142 | <BR>In <EM>Proceedings of the Design Automation Conference</EM>, pages |
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| 143 | 272-277, Dallas, TX, June 1993. |
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| 144 | |
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| 145 | <P></P><DT><A NAME="Panda95b">13</A> |
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| 146 | <DD> |
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| 147 | S. Panda and F. Somenzi. |
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| 148 | <BR>Who are the variables in your neighborhood. |
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| 149 | <BR>In <EM>Proceedings of the International Conference on Computer-Aided |
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| 150 | Design</EM>, pages 74-77, San Jose, CA, November 1995. |
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| 151 | |
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| 152 | <P></P><DT><A NAME="Panda94">14</A> |
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| 153 | <DD> |
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| 154 | S. Panda, F. Somenzi, and B. F. Plessier. |
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| 155 | <BR>Symmetry detection and dynamic variable ordering of decision |
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| 156 | diagrams. |
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| 157 | <BR>In <EM>Proceedings of the International Conference on Computer-Aided |
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| 158 | Design</EM>, pages 628-631, San Jose, CA, November 1994. |
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| 159 | |
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| 160 | <P></P><DT><A NAME="Plessi93">15</A> |
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| 161 | <DD> |
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| 162 | B. F. Plessier. |
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| 163 | <BR><EM>A General Framework for Verification of Sequential Circuits</EM>. |
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| 164 | <BR>PhD thesis, University of Colorado at Boulder, Dept. of Electrical |
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| 165 | and Computer Engineering, 1993. |
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| 166 | |
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| 167 | <P></P><DT><A NAME="Rudell93">16</A> |
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| 168 | <DD> |
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| 169 | R. Rudell. |
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| 170 | <BR>Dynamic variable ordering for ordered binary decision diagrams. |
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| 171 | <BR>In <EM>Proceedings of the International Conference on Computer-Aided |
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| 172 | Design</EM>, pages 42-47, Santa Clara, CA, November 1993. |
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| 173 | |
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| 174 | <P></P><DT><A NAME="Sentov92">17</A> |
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| 175 | <DD> |
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| 176 | E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and |
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| 177 | A. Sangiovanni-Vincentelli. |
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| 178 | <BR>Sequential circuit design using synthesis and optimization. |
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| 179 | <BR>In <EM>Proceedings of the International Conference on Computer |
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| 180 | Design</EM>, pages 328-333, Cambridge, MA, October 1992. |
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| 181 | </DL> |
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| 182 | <A NAME="1416"></A> |
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| 188 | |
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| 189 | <P> |
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| 190 | <BR><HR> |
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| 191 | <ADDRESS> |
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| 192 | Fabio Somenzi |
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| 193 | 2005-05-17 |
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| 194 | </ADDRESS> |
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