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57
58<H2><A NAME="SECTION00070000000000000000">
59Bibliography</A>
60</H2><DL COMPACT><DD><P></P><DT><A NAME="Bahar93">1</A>
61<DD>
62R.&nbsp;I. Bahar, E.&nbsp;A. Frohm, C.&nbsp;M. Gaona, G.&nbsp;D. Hachtel, E.&nbsp;Macii, A.&nbsp;Pardo, and
63  F.&nbsp;Somenzi.
64<BR>Algebraic decision diagrams and their applications.
65<BR>In <EM>Proceedings of the International Conference on Computer-Aided
66  Design</EM>, pages 188-191, Santa Clara, CA, November 1993.
67
68<P></P><DT><A NAME="Bollig95">2</A>
69<DD>
70B.&nbsp;Bollig, M.&nbsp;L&#246;bbing, and I.&nbsp;Wegener.
71<BR>Simulated annealing to improve variable orderings for OBDDs.
72<BR>Presented at the International Workshop on Logic Synthesis,
73  Granlibakken, CA, May 1995.
74
75<P></P><DT><A NAME="BBR">3</A>
76<DD>
77K.&nbsp;S. Brace, R.&nbsp;L. Rudell, and R.&nbsp;E. Bryant.
78<BR>Efficient implementation of a BDD package.
79<BR>In <EM>Proceedings of the 27th Design Automation Conference</EM>, pages
80  40-45, Orlando, FL, June 1990.
81
82<P></P><DT><A NAME="VIS">4</A>
83<DD>
84R.&nbsp;K. Brayton et&nbsp;al.
85<BR>VIS: A system for verification and synthesis.
86<BR>Technical Report UCB/ERL M95/104, Electronics Research Lab, Univ. of
87  California, December 1995.
88
89<P></P><DT><A NAME="BDD">5</A>
90<DD>
91R.&nbsp;E. Bryant.
92<BR>Graph-based algorithms for Boolean function manipulation.
93<BR><EM>IEEE Transactions on Computers</EM>, C-35(8):677-691, August 1986.
94
95<P></P><DT><A NAME="Drechs95">6</A>
96<DD>
97R.&nbsp;Drechsler, B.&nbsp;Becker, and N.&nbsp;G&#246;ckel.
98<BR>A genetic algorithm for variable ordering of OBDDs.
99<BR>Presented at the International Workshop on Logic Synthesis,
100  Granlibakken, CA, May 1995.
101
102<P></P><DT><A NAME="Friedman90">7</A>
103<DD>
104S.&nbsp;J. Friedman and K.&nbsp;J. Supowit.
105<BR>Finding the optimal variable ordering for binary decision diagrams.
106<BR><EM>IEEE Transactions on Computers</EM>, 39(5):710-713, May 1990.
107
108<P></P><DT><A NAME="Fujita91b">8</A>
109<DD>
110M.&nbsp;Fujita, Y.&nbsp;Matsunaga, and T.&nbsp;Kakuda.
111<BR>On variable ordering of binary decision diagrams for the application
112  of multi-level logic synthesis.
113<BR>In <EM>Proceedings of the European Conference on Design Automation</EM>,
114  pages 50-54, Amsterdam, February 1991.
115
116<P></P><DT><A NAME="Held62">9</A>
117<DD>
118M.&nbsp;Held and R.&nbsp;M. Karp.
119<BR>A dynamic programming approach to sequencing problems.
120<BR><EM>J. SIAM</EM>, 10(1):196-210, 1962.
121
122<P></P><DT><A NAME="Ishiur91">10</A>
123<DD>
124N.&nbsp;Ishiura, H.&nbsp;Sawada, and S.&nbsp;Yajima.
125<BR>Minimization of binary decision diagrams based on exchanges of
126  variables.
127<BR>In <EM>Proceedings of the International Conference on Computer-Aided
128  Design</EM>, pages 472-475, Santa Clara, CA, November 1991.
129
130<P></P><DT><A NAME="Jeong93">11</A>
131<DD>
132S.-W. Jeong, T.-S. Kim, and F.&nbsp;Somenzi.
133<BR>An efficient method for optimal BDD ordering computation.
134<BR>In <EM>International Conference on VLSI and CAD (ICVC'93)</EM>, Taejon,
135  Korea, November 1993.
136
137<P></P><DT><A NAME="Minato93">12</A>
138<DD>
139S.-I. Minato.
140<BR>Zero-suppressed BDDs for set manipulation in combinatorial
141  problems.
142<BR>In <EM>Proceedings of the Design Automation Conference</EM>, pages
143  272-277, Dallas, TX, June 1993.
144
145<P></P><DT><A NAME="Panda95b">13</A>
146<DD>
147S.&nbsp;Panda and F.&nbsp;Somenzi.
148<BR>Who are the variables in your neighborhood.
149<BR>In <EM>Proceedings of the International Conference on Computer-Aided
150  Design</EM>, pages 74-77, San Jose, CA, November 1995.
151
152<P></P><DT><A NAME="Panda94">14</A>
153<DD>
154S.&nbsp;Panda, F.&nbsp;Somenzi, and B.&nbsp;F. Plessier.
155<BR>Symmetry detection and dynamic variable ordering of decision
156  diagrams.
157<BR>In <EM>Proceedings of the International Conference on Computer-Aided
158  Design</EM>, pages 628-631, San Jose, CA, November 1994.
159
160<P></P><DT><A NAME="Plessi93">15</A>
161<DD>
162B.&nbsp;F. Plessier.
163<BR><EM>A General Framework for Verification of Sequential Circuits</EM>.
164<BR>PhD thesis, University of Colorado at Boulder, Dept. of Electrical
165  and Computer Engineering, 1993.
166
167<P></P><DT><A NAME="Rudell93">16</A>
168<DD>
169R.&nbsp;Rudell.
170<BR>Dynamic variable ordering for ordered binary decision diagrams.
171<BR>In <EM>Proceedings of the International Conference on Computer-Aided
172  Design</EM>, pages 42-47, Santa Clara, CA, November 1993.
173
174<P></P><DT><A NAME="Sentov92">17</A>
175<DD>
176E.&nbsp;M. Sentovich, K.&nbsp;J. Singh, C.&nbsp;Moon, H.&nbsp;Savoj, R.&nbsp;K. Brayton, and
177  A.&nbsp;Sangiovanni-Vincentelli.
178<BR>Sequential circuit design using synthesis and optimization.
179<BR>In <EM>Proceedings of the International Conference on Computer
180  Design</EM>, pages 328-333, Cambridge, MA, October 1992.
181</DL>
182<A NAME="1416"></A>
183<A NAME="1417"></A>
184<A NAME="1418"></A>
185<A NAME="1419"></A>
186<A NAME="1420"></A>
187<A NAME="1421"></A>
188
189<P>
190<BR><HR>
191<ADDRESS>
192Fabio Somenzi
1932005-05-17
194</ADDRESS>
195</BODY>
196</HTML>
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