[11] | 1 | typedef enum {A, B, C, X} selection; |
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| 2 | typedef enum {IDLE, READY, BUSY} controller_state; |
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| 3 | typedef enum {NO_REQ, REQ, HAVE_TOKEN} client_state; |
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| 4 | |
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| 5 | module main(clk); |
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| 6 | input clk; |
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| 7 | output ackA, ackB, ackC; |
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| 8 | |
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| 9 | selection wire sel; |
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| 10 | wire active; |
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| 11 | |
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| 12 | assign active = pass_tokenA || pass_tokenB || pass_tokenC; |
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| 13 | |
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| 14 | controller controllerA(clk, reqA, ackA, sel, pass_tokenA, A); |
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| 15 | controller controllerB(clk, reqB, ackB, sel, pass_tokenB, B); |
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| 16 | controller controllerC(clk, reqC, ackC, sel, pass_tokenC, C); |
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| 17 | arbiter arbiter(clk, sel, active); |
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| 18 | |
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| 19 | client clientA(clk, reqA, ackA); |
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| 20 | client clientB(clk, reqB, ackB); |
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| 21 | client clientC(clk, reqC, ackC); |
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| 22 | |
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| 23 | observer observer(clk, reqA, ackA); |
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| 24 | |
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| 25 | endmodule |
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| 26 | |
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| 27 | module controller(clk, req, ack, sel, pass_token, id); |
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| 28 | input clk, req, sel, id; |
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| 29 | output ack, pass_token; |
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| 30 | |
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| 31 | selection wire sel, id; |
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| 32 | reg ack, pass_token; |
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| 33 | controller_state reg state; |
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| 34 | |
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| 35 | initial state = IDLE; |
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| 36 | initial ack = 0; |
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| 37 | initial pass_token = 1; |
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| 38 | |
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| 39 | wire is_selected; |
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| 40 | assign is_selected = (sel == id); |
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| 41 | |
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| 42 | always @(posedge clk) begin |
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| 43 | case(state) |
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| 44 | IDLE: |
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| 45 | if (is_selected) |
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| 46 | if (req) |
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| 47 | begin |
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| 48 | state = READY; |
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| 49 | pass_token = 0; /* dropping off this line causes a safety bug */ |
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| 50 | end |
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| 51 | else |
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| 52 | pass_token = 1; |
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| 53 | else |
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| 54 | pass_token = 0; |
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| 55 | READY: |
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| 56 | begin |
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| 57 | state = BUSY; |
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| 58 | ack = 1; |
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| 59 | end |
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| 60 | BUSY: |
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| 61 | if (!req) |
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| 62 | begin |
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| 63 | state = IDLE; |
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| 64 | ack = 0; |
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| 65 | pass_token = 1; |
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| 66 | end |
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| 67 | endcase |
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| 68 | end |
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| 69 | endmodule |
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| 70 | |
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| 71 | module arbiter(clk, sel, active); |
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| 72 | input clk, active; |
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| 73 | output sel; |
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| 74 | |
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| 75 | selection wire sel; |
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| 76 | selection reg state; |
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| 77 | |
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| 78 | initial state = A; |
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| 79 | |
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| 80 | assign sel = active ? state: X; |
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| 81 | |
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| 82 | always @(posedge clk) begin |
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| 83 | if (active) |
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| 84 | case(state) |
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| 85 | A: |
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| 86 | state = B; |
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| 87 | B: |
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| 88 | state = C; |
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| 89 | C: |
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| 90 | state = A; |
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| 91 | endcase |
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| 92 | end |
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| 93 | endmodule |
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| 94 | |
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| 95 | module client(clk, req, ack); |
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| 96 | input clk, ack; |
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| 97 | output req; |
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| 98 | |
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| 99 | reg req; |
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| 100 | client_state reg state; |
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| 101 | |
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| 102 | wire rand_choice; |
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| 103 | |
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| 104 | initial req = 0; |
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| 105 | initial state = NO_REQ; |
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| 106 | |
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| 107 | assign rand_choice = $ND(0,1); |
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| 108 | |
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| 109 | always @(posedge clk) begin |
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| 110 | case(state) |
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| 111 | NO_REQ: |
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| 112 | if (rand_choice) |
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| 113 | begin |
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| 114 | req = 1; |
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| 115 | state = REQ; |
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| 116 | end |
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| 117 | REQ: |
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| 118 | if (ack) |
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| 119 | state = HAVE_TOKEN; |
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| 120 | HAVE_TOKEN: |
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| 121 | if (rand_choice) |
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| 122 | begin |
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| 123 | req = 0; |
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| 124 | state = NO_REQ; |
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| 125 | end |
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| 126 | endcase |
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| 127 | end |
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| 128 | endmodule |
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| 129 | |
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| 130 | typedef enum {IDLE, BAD, GOOD} observer_state; |
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| 131 | |
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| 132 | module observer(clk, req, ack); |
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| 133 | input clk, req, ack; |
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| 134 | |
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| 135 | observer_state reg state; |
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| 136 | initial state = IDLE; |
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| 137 | |
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| 138 | wire rand_choice; |
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| 139 | assign rand_choice = $ND(0,1); |
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| 140 | |
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| 141 | always @(posedge clk) begin |
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| 142 | case(state) |
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| 143 | IDLE: |
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| 144 | if (req && rand_choice) |
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| 145 | state = BAD; |
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| 146 | BAD: |
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| 147 | if (ack) |
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| 148 | state = GOOD; |
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| 149 | endcase |
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| 150 | end |
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| 151 | endmodule |
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