[11] | 1 | module CACHE_CTRLER ( |
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| 2 | clk, |
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| 3 | read_req, write_req, data, address, // input: requests from processor |
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| 4 | acknowledge, // output: to processor |
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| 5 | write_back_req, inval, blocknum, // input: requests from directory |
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| 6 | blk_ok, blk_data, // input: answers from directory |
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| 7 | back_data, cache_req,blk_add, // output: to directory |
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| 8 | ); |
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| 9 | |
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| 10 | input clk; |
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| 11 | input read_req, write_req, data; // input: requests from processor |
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| 12 | input [`address_size:0] address; // input: requests from processor |
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| 13 | input [`address_size:0] blocknum; // input: requests from directory |
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| 14 | input write_back_req, inval; // input: requests from directory |
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| 15 | input blk_ok, blk_data; // input: answers from directory |
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| 16 | output acknowledge; // output: to processor |
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| 17 | output back_data; // output: to directory |
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| 18 | output cache_req; // output: to directory |
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| 19 | output [`address_size:0] blk_add; // output: to directory |
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| 20 | |
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| 21 | Cache_reqstatus reg cache_req; |
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| 22 | wire back_data; |
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| 23 | wire acknowledge; |
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| 24 | reg blk_add; |
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| 25 | |
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| 26 | |
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| 27 | // Registers local to the cache controler |
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| 28 | Block_status reg block_state; |
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| 29 | Cache_status reg cache_state; |
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| 30 | reg [`address_size:0] block_add; // memory address of the block |
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| 31 | reg block_val; // value of the block |
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| 32 | |
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| 33 | initial begin |
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| 34 | cache_state = Ready; |
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| 35 | block_state = INVALID; |
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| 36 | block_add = 0; |
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| 37 | block_val = 0; |
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| 38 | blk_add = 0; |
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| 39 | cache_req = noop; |
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| 40 | end |
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| 41 | |
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| 42 | assign back_data =(cache_req==ok)?block_val:0; |
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| 43 | assign acknowledge = ((cache_state == Rgrant)||(cache_state == Wgrant))?1:0; |
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| 44 | |
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| 45 | always @(posedge clk) begin |
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| 46 | |
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| 47 | |
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| 48 | case ( cache_state ) |
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| 49 | Ready: begin //ready to service a directory request |
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| 50 | if ((inval)&&(block_add ==blocknum)) // block invalidation request |
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| 51 | begin |
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| 52 | block_state = INVALID ; |
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| 53 | cache_req = ok; |
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| 54 | cache_state = Ready; |
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| 55 | end |
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| 56 | else if (write_back_req) |
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| 57 | begin |
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| 58 | block_state = SHARED ; |
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| 59 | cache_req = ok; |
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| 60 | cache_state = Ready; |
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| 61 | end |
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| 62 | else if (read_req) |
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| 63 | begin |
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| 64 | if ((block_add != address) || (block_state == INVALID)) |
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| 65 | begin // read miss |
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| 66 | cache_req = blk_rreq; // ask to read block from memory |
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| 67 | blk_add = address; |
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| 68 | cache_state = Rwait; |
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| 69 | block_state = INVALID; //invalidates if replacement |
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| 70 | end |
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| 71 | else |
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| 72 | begin // read hit |
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| 73 | cache_state = Rgrant; |
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| 74 | cache_req = noop; |
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| 75 | end |
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| 76 | end |
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| 77 | else if (write_req) |
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| 78 | begin |
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| 79 | if ((block_add != address) || (block_state != EXCLUSIVE)) |
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| 80 | begin // write miss |
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| 81 | cache_req = blk_excl; // ask exclusive block from memory |
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| 82 | blk_add = address; |
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| 83 | cache_state = Wwait; |
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| 84 | block_state = INVALID; //invalidates if replacement |
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| 85 | end |
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| 86 | else |
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| 87 | begin // write hit |
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| 88 | cache_state = Wgrant; |
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| 89 | cache_req = noop; |
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| 90 | end |
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| 91 | end |
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| 92 | else |
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| 93 | begin |
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| 94 | cache_req = noop; |
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| 95 | blk_add = 0; |
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| 96 | end |
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| 97 | end |
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| 98 | |
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| 99 | Rgrant: begin // read acknowledge to processor |
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| 100 | if ((inval)&&(block_add == blocknum)) |
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| 101 | begin |
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| 102 | block_state = INVALID; |
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| 103 | cache_req = ok; |
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| 104 | cache_state = Ready; |
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| 105 | end |
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| 106 | else |
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| 107 | begin |
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| 108 | cache_state = Ready; |
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| 109 | end |
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| 110 | end |
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| 111 | |
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| 112 | Wgrant: begin |
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| 113 | if ((inval)&&(block_add == blocknum)) |
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| 114 | begin |
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| 115 | block_state = INVALID; |
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| 116 | cache_req = ok; |
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| 117 | cache_state = Ready; |
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| 118 | end |
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| 119 | else |
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| 120 | begin |
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| 121 | block_val = data; |
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| 122 | cache_state = Ready; |
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| 123 | end |
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| 124 | end |
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| 125 | |
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| 126 | Rwait: begin |
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| 127 | if ((inval)&&(block_add == blocknum)) |
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| 128 | begin |
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| 129 | block_state = INVALID; |
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| 130 | cache_req = ok; |
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| 131 | cache_state = Ready; |
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| 132 | end |
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| 133 | else if (write_back_req) |
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| 134 | begin |
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| 135 | cache_state = Ready; |
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| 136 | //cache_req = ok; |
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| 137 | end |
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| 138 | else if ( blk_ok ) |
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| 139 | begin |
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| 140 | block_val = blk_data; |
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| 141 | block_add = blk_add; |
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| 142 | block_state = SHARED; |
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| 143 | cache_req = noop; |
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| 144 | cache_state = Rgrant; |
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| 145 | end |
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| 146 | else cache_state = Rwait; |
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| 147 | end |
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| 148 | |
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| 149 | Wwait: begin |
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| 150 | if ((inval)&&(block_add == blocknum)) |
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| 151 | begin |
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| 152 | block_state = INVALID; |
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| 153 | cache_req = ok; |
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| 154 | cache_state = Ready; |
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| 155 | end |
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| 156 | else if (write_back_req) |
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| 157 | begin |
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| 158 | cache_state = Ready; |
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| 159 | //cache_req = ok; |
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| 160 | end |
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| 161 | else if ( blk_ok ) |
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| 162 | begin |
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| 163 | block_val = blk_data; |
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| 164 | block_add = blk_add; |
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| 165 | block_state = EXCLUSIVE; |
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| 166 | cache_req = noop; |
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| 167 | cache_state = Wgrant; |
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| 168 | end |
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| 169 | else cache_state = Wwait; |
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| 170 | end |
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| 171 | |
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| 172 | default: cache_req = noop; |
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| 173 | endcase; |
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| 174 | end // end of always statement describing cache controller automaton |
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| 175 | endmodule |
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