[11] | 1 | `define address_size 0 // nb of bits - 1 of addressÊof blocs in memory |
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| 2 | `define mem_size 1 // number of blocks in memory - 1 |
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| 3 | |
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| 4 | typedef enum {INVALID, SHARED, EXCLUSIVE} Block_status; |
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| 5 | typedef enum { Ready, Rwait, Wwait, Rgrant, Wgrant} |
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| 6 | Cache_status; |
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| 7 | typedef enum { COMPUTE, READ_WORD, WRITE_WORD } Instruction_type; |
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| 8 | typedef enum { IDLE, READING, WRITING } Processor_state; |
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| 9 | typedef enum { ONE, ONEWAIT,TWO, TWOWAIT, ONESERVE, TWOSERVE} Arbiter_status; |
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| 10 | // typedef enum { HIT,MISS,NOP} Cache_rwtype; |
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| 11 | typedef enum {ok, blk_rreq, blk_excl, noop} Cache_reqstatus; |
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| 12 | |
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| 13 | // This is the main module |
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| 14 | // It has 3 types of sub,modules |
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| 15 | |
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| 16 | module COHERANCE(clk, |
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| 17 | any_address1, any_value1,inst1, //address, data, instruction for 1 |
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| 18 | any_address2, any_value2,inst2); |
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| 19 | |
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| 20 | |
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| 21 | input [`address_size:0] any_address1; |
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| 22 | input [`address_size:0] any_address2; |
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| 23 | input any_value1; |
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| 24 | input any_value2; |
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| 25 | input inst1; |
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| 26 | input inst2; |
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| 27 | input clk; |
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| 28 | |
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| 29 | |
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| 30 | wire acknowledge1; // output: to processor |
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| 31 | wire read_req1, write_req1, data1; // input: requests from processor |
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| 32 | wire [`address_size:0] address1; // input: requests from processor |
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| 33 | Instruction_type wire inst1; |
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| 34 | wire acknowledge2; // output: to processor |
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| 35 | wire read_req2, write_req2, data2; // input: requests from processor |
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| 36 | wire [`address_size:0] address2; // input: requests from processor |
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| 37 | Instruction_type wire inst2; |
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| 38 | wire back_data; |
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| 39 | wire blk_add1; |
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| 40 | wire blk_add2; |
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| 41 | wire blk_data; |
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| 42 | wire write_back_req1; |
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| 43 | wire write_back_req2; |
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| 44 | wire blk_ok1; |
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| 45 | wire blk_ok2; |
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| 46 | wire inval1; |
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| 47 | wire inval2; |
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| 48 | wire inval3; |
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| 49 | wire [`address_size:0] blocknum; |
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| 50 | wire wbr1; |
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| 51 | wire wbr2; |
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| 52 | Cache_reqstatus wire cache_req1; |
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| 53 | Cache_reqstatus wire cache_req2; |
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| 54 | |
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| 55 | |
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| 56 | PROC proc1(clk, read_req1, write_req1, data1, address1, acknowledge1, any_address1, any_value1, inst1); |
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| 57 | CACHE_CTRLER cc1(clk,read_req1, write_req1, data1, address1,acknowledge1,write_back_req1, inval1, blocknum,blk_ok1, blk_data,back_data1, cache_req1,blk_add1); |
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| 58 | |
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| 59 | PROC proc2(clk, read_req2, write_req2, data2, address2, acknowledge2, any_address2, any_value2, inst2); |
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| 60 | CACHE_CTRLER cc2(clk,read_req2, write_req2, data2, address2,acknowledge2,write_back_req2, inval2, blocknum,blk_ok2, blk_data,back_data2, cache_req2,blk_add2); |
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| 61 | |
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| 62 | DIRECTORY direc(clk,write_back_req1, inval1,write_back_req2, inval2,blocknum, blk_ok1, blk_data,blk_ok2, back_data1, cache_req1, blk_add1,back_data2, cache_req2, blk_add2); |
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| 63 | |
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| 64 | endmodule |
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| 65 | `include cache_ctrl.v |
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| 66 | `include processor.v |
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| 67 | `include directory.v |
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| 68 | |
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| 69 | |
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| 70 | |
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| 71 | |
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| 72 | |
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| 73 | |
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| 74 | |
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