Rev | Line | |
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[11] | 1 | #The directory contains information about the cache content |
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| 2 | #that is coherent with the information in the cache controller |
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| 3 | # If the block is in state SHARED in the cache controller, its corresponding |
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| 4 | # bit is set in the Rlist of the directory |
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| 5 | |
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| 6 | AG(((direc.cache_Rlist1<*1*> = 1) -> AX((cc1.block_state=SHARED) * (cc1.block_add<0>=1))) + ((((cc1.block_state=SHARED) * (cc1.block_add<0>=1))) -> (direc.cache_Rlist1<*1*> = 1))); |
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| 7 | |
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| 8 | |
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| 9 | |
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