source: vis_dev/vis-2.1/examples/ctlp3/ctlp3.v @ 16

Last change on this file since 16 was 11, checked in by cecile, 13 years ago

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[11]1/* Dining philosophers of E. W. Dijkstra
2        based on S/R implementation by R. Kurshan
3        Ramin Hojati, May 1993
4
5*/
6typedef enum {THINKING, HUNGRY, EATING, READING} t_state;
7
8/************************************************************************/
9module diners(clk);
10input clk;
11
12t_state wire s0, s1, s2;
13
14philosopher ph0(clk, s0, s1, s2, EATING);
15philosopher ph1(clk, s1, s2, s0, READING);
16philosopher ph2(clk, s2, s0, s1, HUNGRY);
17
18starvation str(clk, s0);
19
20endmodule
21
22/************************************************************************/
23module philosopher(clk, out, left, right, init);
24input clk;
25input left, right, init;
26output out;
27t_state wire left, right, init, out;
28t_state reg state;
29t_state wire r0_state,r1_state;
30
31
32initial state = init;
33
34assign r0_state = $ND(THINKING,HUNGRY);
35assign r1_state = $ND(THINKING,EATING);
36assign out = state;
37
38always @(posedge clk) begin
39    case(state)
40        READING:
41                if (left == THINKING) state = THINKING;
42
43        THINKING:
44            begin
45                if ( right == READING ) state = READING;
46                else state = r0_state; 
47            end
48   
49        EATING:
50                  state = r1_state; 
51
52        HUNGRY:
53                if ( left != EATING && right != HUNGRY && right != EATING) 
54                state = EATING; 
55        endcase
56end
57endmodule
58
59/************************************************************************/
60module starvation( clk, starv );
61        input   clk;
62        input   starv;
63        t_state wire starv;
64        reg     state;
65
66initial state = 0;
67
68always @(posedge clk) begin
69    case(state) 
70        0: if ( starv == HUNGRY ) state = 1;
71
72        1: if ( starv == THINKING ) state = 0;
73
74    endcase
75end
76endmodule       
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