| 1 | # vl2mv dcnew.v |
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| 2 | # version: 0.2 |
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| 3 | # date: 11:13:36 12/11/95 (PST) |
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| 4 | .model dchek |
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| 5 | # I/O ports |
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| 6 | |
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| 7 | .mv interpretation 2 go stop |
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| 8 | .mv charger 2 discharged charged |
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| 9 | .mv ts_power 2 on off |
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| 10 | .mv track3 2 conduct open |
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| 11 | .mv train 3 present1 present2 absent |
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| 12 | .mv contact 3 B middle C |
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| 13 | .mv lamp 2 lit unlit |
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| 14 | .mv relay 2 pulling neutral |
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| 15 | .mv track2 2 conduct open |
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| 16 | .mv track1 2 conduct open |
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| 17 | .subckt track_mod trk1 track=track1 |
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| 18 | .subckt track_mod trk2 track=track2 |
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| 19 | .subckt track_mod trk3 track=track3 |
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| 20 | .subckt charger_mod chg ts_power=ts_power lamp=lamp out=charger |
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| 21 | .subckt relay_mod rly charger=charger relay=relay |
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| 22 | .subckt lamp_mod lmp contact=contact wire3=track3 ts_power=ts_power charger=charger lamp=lamp |
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| 23 | .subckt contact_mod cnt relay=relay contact=contact |
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| 24 | .subckt train_mod trn out=train |
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| 25 | .subckt track_system_mod tsm wire1=track1 wire2=track2 train=train contact=contact ts_power=ts_power |
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| 26 | .subckt interpretation_mod int lamp=lamp out=interpretation |
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| 27 | .subckt property_mod prop train=train interpretation=interpretation |
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| 28 | # conflict arbitrators |
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| 29 | # non-blocking assignments |
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| 30 | # latches |
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| 31 | # quasi-continuous assignment |
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| 32 | .end |
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| 33 | |
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| 34 | |
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| 35 | .model track_mod |
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| 36 | # I/O ports |
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| 37 | .outputs track |
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| 38 | |
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| 39 | .mv r_state 3 good faulty1 faulty2 |
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| 40 | .mv state 3 good faulty1 faulty2 |
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| 41 | .mv track 2 conduct open |
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| 42 | # state = 0 |
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| 43 | .mv state$raw_n0 3 good faulty1 faulty2 |
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| 44 | .names state$raw_n0 |
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| 45 | good |
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| 46 | # non-blocking assignments for initial |
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| 47 | # assign r_state = $NDset ( 0,1 ) |
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| 48 | .names r_state |
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| 49 | good |
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| 50 | faulty1 |
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| 51 | # assign track = (state == good ) ? 0 : 1 |
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| 52 | .mv track$raw_n3 2 conduct open |
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| 53 | .mv _n5 3 good faulty1 faulty2 |
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| 54 | .names _n5 |
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| 55 | good |
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| 56 | # state == 0 |
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| 57 | .names state _n5 _n4 |
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| 58 | .def 0 |
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| 59 | - =state 1 |
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| 60 | .mv _n6 2 conduct open |
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| 61 | .names _n6 |
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| 62 | conduct |
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| 63 | .mv _n7 2 conduct open |
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| 64 | .names _n7 |
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| 65 | open |
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| 66 | # (state == 0) ? 0 : 1 |
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| 67 | .mv _n8 2 conduct open |
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| 68 | .names _n6 _n7 _n4 _n8 |
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| 69 | - - 0 =_n7 |
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| 70 | - - 1 =_n6 |
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| 71 | .names _n8 track$raw_n3 |
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| 72 | - =_n8 |
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| 73 | .mv _na 3 good faulty1 faulty2 |
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| 74 | .names _na |
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| 75 | faulty1 |
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| 76 | # state == 1 |
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| 77 | .names state _na _n9 |
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| 78 | .def 0 |
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| 79 | - =state 1 |
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| 80 | .names _n9 _nb |
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| 81 | - =_n9 |
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| 82 | # state = 1 |
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| 83 | .mv state$_n9_nc$true 3 good faulty1 faulty2 |
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| 84 | .names state$_n9_nc$true |
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| 85 | faulty1 |
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| 86 | # if/else (state == 1) |
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| 87 | .mv state$_n9$raw_nf 3 good faulty1 faulty2 |
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| 88 | .names state$_n9_nc$true state _n9 state$_n9$raw_nf |
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| 89 | - - 0 =state |
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| 90 | - - 1 =state$_n9_nc$true |
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| 91 | .mv _n11 3 good faulty1 faulty2 |
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| 92 | .names _n11 |
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| 93 | good |
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| 94 | # state == 0 |
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| 95 | .names state$_n9$raw_nf _n11 _n10 |
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| 96 | .def 0 |
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| 97 | - =state$_n9$raw_nf 1 |
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| 98 | .names _n10 _n12 |
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| 99 | - =_n10 |
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| 100 | # state = r_state |
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| 101 | .mv state$_n10_n13$true 3 good faulty1 faulty2 |
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| 102 | .names r_state state$_n10_n13$true |
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| 103 | - =r_state |
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| 104 | # if/else (state == 0) |
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| 105 | .mv state$_n10$raw_n14 3 good faulty1 faulty2 |
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| 106 | .names state$_n10_n13$true state$_n9$raw_nf _n10 state$_n10$raw_n14 |
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| 107 | - - 0 =state$_n9$raw_nf |
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| 108 | - - 1 =state$_n10_n13$true |
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| 109 | # conflict arbitrators |
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| 110 | .names _nb _n12 _n18 |
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| 111 | .def 0 |
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| 112 | 1 - 1 |
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| 113 | - 1 1 |
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| 114 | .mv _n19 3 good faulty1 faulty2 |
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| 115 | .names _n18 state$_n10$raw_n14 state _n19 |
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| 116 | 1 - - =state$_n10$raw_n14 |
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| 117 | 0 - - =state |
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| 118 | .names track$raw_n3 track |
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| 119 | - =track$raw_n3 |
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| 120 | # non-blocking assignments |
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| 121 | # latches |
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| 122 | .r state$raw_n0 state |
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| 123 | - =state$raw_n0 |
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| 124 | .latch _n19 state |
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| 125 | # quasi-continuous assignment |
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| 126 | .end |
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| 127 | |
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| 128 | |
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| 129 | .model charger_mod |
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| 130 | # I/O ports |
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| 131 | .outputs out |
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| 132 | .inputs ts_power |
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| 133 | .inputs lamp |
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| 134 | |
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| 135 | .mv out 2 discharged charged |
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| 136 | .mv charger 2 discharged charged |
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| 137 | .mv r_state 3 good faulty1 faulty2 |
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| 138 | .mv state 3 good faulty1 faulty2 |
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| 139 | .mv ts_power 2 on off |
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| 140 | .mv lamp 2 lit unlit |
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| 141 | # state = 0 |
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| 142 | .mv state$raw_n1e 3 good faulty1 faulty2 |
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| 143 | .names state$raw_n1e |
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| 144 | good |
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| 145 | # non-blocking assignments for initial |
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| 146 | # charger = 0 |
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| 147 | .mv charger$raw_n1f 2 discharged charged |
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| 148 | .names charger$raw_n1f |
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| 149 | discharged |
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| 150 | # non-blocking assignments for initial |
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| 151 | # assign r_state = $NDset ( 0,1,2 ) |
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| 152 | .names r_state |
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| 153 | good |
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| 154 | faulty1 |
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| 155 | faulty2 |
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| 156 | # assign out = state == faulty1 ? 0 : state == faulty2 ? 1 : charger |
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| 157 | .mv out$raw_n22 2 discharged charged |
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| 158 | .mv _n24 3 good faulty1 faulty2 |
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| 159 | .names _n24 |
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| 160 | faulty1 |
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| 161 | # state == 1 |
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| 162 | .names state _n24 _n23 |
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| 163 | .def 0 |
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| 164 | - =state 1 |
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| 165 | .mv _n26 3 good faulty1 faulty2 |
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| 166 | .names _n26 |
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| 167 | faulty2 |
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| 168 | # state == 2 |
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| 169 | .names state _n26 _n25 |
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| 170 | .def 0 |
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| 171 | - =state 1 |
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| 172 | .mv _n27 2 discharged charged |
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| 173 | .names _n27 |
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| 174 | charged |
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| 175 | # state == 2 ? 1 : charger |
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| 176 | .mv _n28 2 discharged charged |
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| 177 | .names _n27 charger _n25 _n28 |
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| 178 | - - 0 =charger |
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| 179 | - - 1 =_n27 |
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| 180 | .mv _n29 2 discharged charged |
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| 181 | .names _n29 |
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| 182 | discharged |
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| 183 | # state == 1 ? 0 : state == 2 ? 1 : charger |
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| 184 | .mv _n2a 2 discharged charged |
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| 185 | .names _n29 _n28 _n23 _n2a |
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| 186 | - - 0 =_n28 |
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| 187 | - - 1 =_n29 |
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| 188 | .names _n2a out$raw_n22 |
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| 189 | - =_n2a |
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| 190 | .mv _n2c 3 good faulty1 faulty2 |
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| 191 | .names _n2c |
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| 192 | faulty1 |
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| 193 | # state == 1 |
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| 194 | .names state _n2c _n2b |
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| 195 | .def 0 |
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| 196 | - =state 1 |
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| 197 | .names _n2b _n2d |
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| 198 | - =_n2b |
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| 199 | # state = 1 |
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| 200 | .mv state$_n2b_n2e$true 3 good faulty1 faulty2 |
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| 201 | .names state$_n2b_n2e$true |
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| 202 | faulty1 |
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| 203 | # if/else (state == 1) |
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| 204 | .mv state$_n2b$raw_n31 3 good faulty1 faulty2 |
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| 205 | .names state$_n2b_n2e$true state _n2b state$_n2b$raw_n31 |
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| 206 | - - 0 =state |
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| 207 | - - 1 =state$_n2b_n2e$true |
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| 208 | .mv _n33 3 good faulty1 faulty2 |
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| 209 | .names _n33 |
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| 210 | faulty2 |
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| 211 | # state == 2 |
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| 212 | .names state$_n2b$raw_n31 _n33 _n32 |
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| 213 | .def 0 |
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| 214 | - =state$_n2b$raw_n31 1 |
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| 215 | .names _n32 _n34 |
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| 216 | - =_n32 |
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| 217 | # state = 2 |
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| 218 | .mv state$_n32_n35$true 3 good faulty1 faulty2 |
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| 219 | .names state$_n32_n35$true |
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| 220 | faulty2 |
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| 221 | # if/else (state == 2) |
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| 222 | .mv state$_n32$raw_n36 3 good faulty1 faulty2 |
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| 223 | .names state$_n32_n35$true state$_n2b$raw_n31 _n32 state$_n32$raw_n36 |
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| 224 | - - 0 =state$_n2b$raw_n31 |
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| 225 | - - 1 =state$_n32_n35$true |
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| 226 | .mv _n3b 3 good faulty1 faulty2 |
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| 227 | .names _n3b |
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| 228 | good |
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| 229 | # state == 0 |
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| 230 | .names state$_n32$raw_n36 _n3b _n3a |
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| 231 | .def 0 |
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| 232 | - =state$_n32$raw_n36 1 |
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| 233 | .names _n3a _n3c |
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| 234 | - =_n3a |
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| 235 | # state = r_state |
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| 236 | .mv state$_n3a_n3d$true 3 good faulty1 faulty2 |
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| 237 | .names r_state state$_n3a_n3d$true |
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| 238 | - =r_state |
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| 239 | .mv _n3f 2 on off |
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| 240 | .names _n3f |
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| 241 | on |
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| 242 | # ts_power == 0 |
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| 243 | .names ts_power _n3f _n3e |
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| 244 | .def 0 |
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| 245 | - =ts_power 1 |
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| 246 | .names _n3e _n40 |
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| 247 | - =_n3e |
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| 248 | # charger = 1 |
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| 249 | .mv charger$_n3e_n41$true 2 discharged charged |
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| 250 | .names charger$_n3e_n41$true |
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| 251 | charged |
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| 252 | .mv _n43 2 lit unlit |
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| 253 | .names _n43 |
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| 254 | lit |
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| 255 | # lamp == 0 |
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| 256 | .names lamp _n43 _n42 |
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| 257 | .def 0 |
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| 258 | - =lamp 1 |
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| 259 | .names _n42 _n44 |
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| 260 | - =_n42 |
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| 261 | # charger = 0 |
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| 262 | .mv charger$_n42_n45$true 2 discharged charged |
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| 263 | .names charger$_n42_n45$true |
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| 264 | discharged |
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| 265 | # charger = charger |
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| 266 | .mv charger$_n42_n46$false 2 discharged charged |
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| 267 | .names charger charger$_n42_n46$false |
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| 268 | - =charger |
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| 269 | # if/else (lamp == 0) |
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| 270 | .mv charger$_n42$raw_n49 2 discharged charged |
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| 271 | .names charger$_n42_n45$true charger$_n42_n46$false _n42 charger$_n42$raw_n49 |
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| 272 | - - 0 =charger$_n42_n46$false |
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| 273 | - - 1 =charger$_n42_n45$true |
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| 274 | # if/else (ts_power == 0) |
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| 275 | .mv charger$_n3e$raw_n51 2 discharged charged |
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| 276 | .names charger$_n3e_n41$true charger$_n42$raw_n49 _n3e charger$_n3e$raw_n51 |
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| 277 | - - 0 =charger$_n42$raw_n49 |
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| 278 | - - 1 =charger$_n3e_n41$true |
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| 279 | # if/else (state == 0) |
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| 280 | .mv state$_n3a$raw_n58 3 good faulty1 faulty2 |
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| 281 | .names state$_n3a_n3d$true state$_n32$raw_n36 _n3a state$_n3a$raw_n58 |
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| 282 | - - 0 =state$_n32$raw_n36 |
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| 283 | - - 1 =state$_n3a_n3d$true |
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| 284 | .mv charger$_n3a$raw_n5b 2 discharged charged |
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| 285 | .names charger$_n3e$raw_n51 charger _n3a charger$_n3a$raw_n5b |
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| 286 | - - 0 =charger |
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| 287 | - - 1 =charger$_n3e$raw_n51 |
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| 288 | # conflict arbitrators |
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| 289 | .names out$raw_n22 out |
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| 290 | - =out$raw_n22 |
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| 291 | .names _n3c _n40 _n44 _n5e |
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| 292 | .def 0 |
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| 293 | 1 1 - 1 |
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| 294 | 1 0 1 1 |
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| 295 | 1 0 0 1 |
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| 296 | .mv _n5f 2 discharged charged |
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| 297 | .names _n5e charger$_n3a$raw_n5b charger _n5f |
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| 298 | 1 - - =charger$_n3a$raw_n5b |
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| 299 | 0 - - =charger |
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| 300 | .names _n2d _n34 _n3c _n66 |
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| 301 | .def 0 |
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| 302 | 1 - - 1 |
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| 303 | - 1 - 1 |
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| 304 | - - 1 1 |
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| 305 | .mv _n67 3 good faulty1 faulty2 |
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| 306 | .names _n66 state$_n3a$raw_n58 state _n67 |
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| 307 | 1 - - =state$_n3a$raw_n58 |
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| 308 | 0 - - =state |
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| 309 | # non-blocking assignments |
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| 310 | # latches |
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| 311 | .r charger$raw_n1f charger |
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| 312 | - =charger$raw_n1f |
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| 313 | .latch _n5f charger |
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| 314 | .r state$raw_n1e state |
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| 315 | - =state$raw_n1e |
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| 316 | .latch _n67 state |
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| 317 | # quasi-continuous assignment |
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| 318 | .end |
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| 319 | |
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| 320 | |
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| 321 | .model relay_mod |
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| 322 | # I/O ports |
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| 323 | .inputs charger |
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| 324 | .outputs relay |
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| 325 | |
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| 326 | .mv charger 2 discharged charged |
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| 327 | .mv r_state 3 good faulty1 faulty2 |
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| 328 | .mv state 3 good faulty1 faulty2 |
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| 329 | .mv relay 2 pulling neutral |
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| 330 | # state = 0 |
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| 331 | .mv state$raw_n6e 3 good faulty1 faulty2 |
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| 332 | .names state$raw_n6e |
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| 333 | good |
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| 334 | # non-blocking assignments for initial |
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| 335 | # assign r_state = $NDset ( 0,1,2 ) |
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| 336 | .names r_state |
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| 337 | good |
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| 338 | faulty1 |
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| 339 | faulty2 |
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| 340 | # assign relay = state == faulty1 ? 1 : state == faulty2 ? 0 : state == good && charger == charged ? 0 : 1 |
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| 341 | .mv relay$raw_n71 2 pulling neutral |
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| 342 | .mv _n73 3 good faulty1 faulty2 |
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| 343 | .names _n73 |
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| 344 | faulty1 |
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| 345 | # state == 1 |
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| 346 | .names state _n73 _n72 |
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| 347 | .def 0 |
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| 348 | - =state 1 |
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| 349 | .mv _n75 3 good faulty1 faulty2 |
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| 350 | .names _n75 |
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| 351 | faulty2 |
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| 352 | # state == 2 |
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| 353 | .names state _n75 _n74 |
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| 354 | .def 0 |
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| 355 | - =state 1 |
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| 356 | .mv _n77 3 good faulty1 faulty2 |
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| 357 | .names _n77 |
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| 358 | good |
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| 359 | # state == 0 |
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| 360 | .names state _n77 _n76 |
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| 361 | .def 0 |
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| 362 | - =state 1 |
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| 363 | .mv _n79 2 discharged charged |
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| 364 | .names _n79 |
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| 365 | charged |
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| 366 | # charger == 1 |
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| 367 | .names charger _n79 _n78 |
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| 368 | .def 0 |
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| 369 | - =charger 1 |
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| 370 | # state == 0 && charger == 1 |
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| 371 | .names _n76 _n78 _n7a |
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| 372 | .def 0 |
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| 373 | 1 1 1 |
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| 374 | .mv _n7b 2 pulling neutral |
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| 375 | .names _n7b |
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| 376 | pulling |
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| 377 | .mv _n7c 2 pulling neutral |
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| 378 | .names _n7c |
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| 379 | neutral |
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| 380 | # state == 0 && charger == 1 ? 0 : 1 |
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| 381 | .mv _n7d 2 pulling neutral |
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| 382 | .names _n7b _n7c _n7a _n7d |
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| 383 | - - 0 =_n7c |
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| 384 | - - 1 =_n7b |
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| 385 | .mv _n7e 2 pulling neutral |
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| 386 | .names _n7e |
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| 387 | pulling |
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| 388 | # state == 2 ? 0 : state == 0 && charger == 1 ? 0 : 1 |
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| 389 | .mv _n7f 2 pulling neutral |
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| 390 | .names _n7e _n7d _n74 _n7f |
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| 391 | - - 0 =_n7d |
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| 392 | - - 1 =_n7e |
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| 393 | .mv _n80 2 pulling neutral |
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| 394 | .names _n80 |
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| 395 | neutral |
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| 396 | # state == 1 ? 1 : state == 2 ? 0 : state == 0 && charger == 1 ? 0 : 1 |
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| 397 | .mv _n81 2 pulling neutral |
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| 398 | .names _n80 _n7f _n72 _n81 |
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| 399 | - - 0 =_n7f |
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| 400 | - - 1 =_n80 |
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| 401 | .names _n81 relay$raw_n71 |
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| 402 | - =_n81 |
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| 403 | .mv _n83 3 good faulty1 faulty2 |
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| 404 | .names _n83 |
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| 405 | faulty1 |
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| 406 | # state == 1 |
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| 407 | .names state _n83 _n82 |
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| 408 | .def 0 |
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| 409 | - =state 1 |
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| 410 | .names _n82 _n84 |
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| 411 | - =_n82 |
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| 412 | # state = 1 |
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| 413 | .mv state$_n82_n85$true 3 good faulty1 faulty2 |
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| 414 | .names state$_n82_n85$true |
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| 415 | faulty1 |
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| 416 | # if/else (state == 1) |
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| 417 | .mv state$_n82$raw_n88 3 good faulty1 faulty2 |
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| 418 | .names state$_n82_n85$true state _n82 state$_n82$raw_n88 |
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| 419 | - - 0 =state |
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| 420 | - - 1 =state$_n82_n85$true |
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| 421 | .mv _n8a 3 good faulty1 faulty2 |
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| 422 | .names _n8a |
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| 423 | faulty2 |
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| 424 | # state == 2 |
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| 425 | .names state$_n82$raw_n88 _n8a _n89 |
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| 426 | .def 0 |
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| 427 | - =state$_n82$raw_n88 1 |
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| 428 | .names _n89 _n8b |
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| 429 | - =_n89 |
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| 430 | # state = 2 |
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| 431 | .mv state$_n89_n8c$true 3 good faulty1 faulty2 |
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| 432 | .names state$_n89_n8c$true |
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| 433 | faulty2 |
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| 434 | # if/else (state == 2) |
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| 435 | .mv state$_n89$raw_n8d 3 good faulty1 faulty2 |
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| 436 | .names state$_n89_n8c$true state$_n82$raw_n88 _n89 state$_n89$raw_n8d |
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| 437 | - - 0 =state$_n82$raw_n88 |
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| 438 | - - 1 =state$_n89_n8c$true |
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| 439 | .mv _n92 3 good faulty1 faulty2 |
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| 440 | .names _n92 |
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| 441 | good |
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| 442 | # state == 0 |
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| 443 | .names state$_n89$raw_n8d _n92 _n91 |
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| 444 | .def 0 |
|---|
| 445 | - =state$_n89$raw_n8d 1 |
|---|
| 446 | .names _n91 _n93 |
|---|
| 447 | - =_n91 |
|---|
| 448 | # state = r_state |
|---|
| 449 | .mv state$_n91_n94$true 3 good faulty1 faulty2 |
|---|
| 450 | .names r_state state$_n91_n94$true |
|---|
| 451 | - =r_state |
|---|
| 452 | # if/else (state == 0) |
|---|
| 453 | .mv state$_n91$raw_n95 3 good faulty1 faulty2 |
|---|
| 454 | .names state$_n91_n94$true state$_n89$raw_n8d _n91 state$_n91$raw_n95 |
|---|
| 455 | - - 0 =state$_n89$raw_n8d |
|---|
| 456 | - - 1 =state$_n91_n94$true |
|---|
| 457 | # conflict arbitrators |
|---|
| 458 | .names _n84 _n8b _n93 _n99 |
|---|
| 459 | .def 0 |
|---|
| 460 | 1 - - 1 |
|---|
| 461 | - 1 - 1 |
|---|
| 462 | - - 1 1 |
|---|
| 463 | .mv _n9a 3 good faulty1 faulty2 |
|---|
| 464 | .names _n99 state$_n91$raw_n95 state _n9a |
|---|
| 465 | 1 - - =state$_n91$raw_n95 |
|---|
| 466 | 0 - - =state |
|---|
| 467 | .names relay$raw_n71 relay |
|---|
| 468 | - =relay$raw_n71 |
|---|
| 469 | # non-blocking assignments |
|---|
| 470 | # latches |
|---|
| 471 | .r state$raw_n6e state |
|---|
| 472 | - =state$raw_n6e |
|---|
| 473 | .latch _n9a state |
|---|
| 474 | # quasi-continuous assignment |
|---|
| 475 | .end |
|---|
| 476 | |
|---|
| 477 | |
|---|
| 478 | .model lamp_mod |
|---|
| 479 | # I/O ports |
|---|
| 480 | .inputs charger |
|---|
| 481 | .inputs wire3 |
|---|
| 482 | .inputs ts_power |
|---|
| 483 | .outputs lamp |
|---|
| 484 | .inputs contact |
|---|
| 485 | |
|---|
| 486 | .mv charger 2 discharged charged |
|---|
| 487 | .mv wire3 2 conduct open |
|---|
| 488 | .mv r_state 3 good faulty1 faulty2 |
|---|
| 489 | .mv state 3 good faulty1 faulty2 |
|---|
| 490 | .mv ts_power 2 on off |
|---|
| 491 | .mv lamp 2 lit unlit |
|---|
| 492 | .mv contact 3 B middle C |
|---|
| 493 | # state = 0 |
|---|
| 494 | .mv state$raw_na0 3 good faulty1 faulty2 |
|---|
| 495 | .names state$raw_na0 |
|---|
| 496 | good |
|---|
| 497 | # non-blocking assignments for initial |
|---|
| 498 | # assign r_state = $NDset ( 0,1,2 ) |
|---|
| 499 | .names r_state |
|---|
| 500 | good |
|---|
| 501 | faulty1 |
|---|
| 502 | faulty2 |
|---|
| 503 | # assign lamp = state == faulty1 ? 1 : state == faulty2 ? 0 : state == good && ((contact == C ) && (wire3 == conduct ) && ((ts_power == on ) | (charger == charged ))) ? 0 : 1 |
|---|
| 504 | .mv lamp$raw_na3 2 lit unlit |
|---|
| 505 | .mv _na5 3 good faulty1 faulty2 |
|---|
| 506 | .names _na5 |
|---|
| 507 | faulty1 |
|---|
| 508 | # state == 1 |
|---|
| 509 | .names state _na5 _na4 |
|---|
| 510 | .def 0 |
|---|
| 511 | - =state 1 |
|---|
| 512 | .mv _na7 3 good faulty1 faulty2 |
|---|
| 513 | .names _na7 |
|---|
| 514 | faulty2 |
|---|
| 515 | # state == 2 |
|---|
| 516 | .names state _na7 _na6 |
|---|
| 517 | .def 0 |
|---|
| 518 | - =state 1 |
|---|
| 519 | .mv _na9 3 good faulty1 faulty2 |
|---|
| 520 | .names _na9 |
|---|
| 521 | good |
|---|
| 522 | # state == 0 |
|---|
| 523 | .names state _na9 _na8 |
|---|
| 524 | .def 0 |
|---|
| 525 | - =state 1 |
|---|
| 526 | .mv _nab 3 B middle C |
|---|
| 527 | .names _nab |
|---|
| 528 | C |
|---|
| 529 | # contact == 2 |
|---|
| 530 | .names contact _nab _naa |
|---|
| 531 | .def 0 |
|---|
| 532 | - =contact 1 |
|---|
| 533 | .mv _nad 2 conduct open |
|---|
| 534 | .names _nad |
|---|
| 535 | conduct |
|---|
| 536 | # wire3 == 0 |
|---|
| 537 | .names wire3 _nad _nac |
|---|
| 538 | .def 0 |
|---|
| 539 | - =wire3 1 |
|---|
| 540 | # (contact == 2) && (wire3 == 0) |
|---|
| 541 | .names _naa _nac _nae |
|---|
| 542 | .def 0 |
|---|
| 543 | 1 1 1 |
|---|
| 544 | .mv _nb0 2 on off |
|---|
| 545 | .names _nb0 |
|---|
| 546 | on |
|---|
| 547 | # ts_power == 0 |
|---|
| 548 | .names ts_power _nb0 _naf |
|---|
| 549 | .def 0 |
|---|
| 550 | - =ts_power 1 |
|---|
| 551 | .mv _nb2 2 discharged charged |
|---|
| 552 | .names _nb2 |
|---|
| 553 | charged |
|---|
| 554 | # charger == 1 |
|---|
| 555 | .names charger _nb2 _nb1 |
|---|
| 556 | .def 0 |
|---|
| 557 | - =charger 1 |
|---|
| 558 | # (ts_power == 0) | (charger == 1) |
|---|
| 559 | .names _naf _nb1 _nb3 |
|---|
| 560 | .def 1 |
|---|
| 561 | 0 0 0 |
|---|
| 562 | # (contact == 2) && (wire3 == 0) && ((ts_power == 0) | (charger == 1)) |
|---|
| 563 | .names _nae _nb3 _nb4 |
|---|
| 564 | .def 0 |
|---|
| 565 | 1 1 1 |
|---|
| 566 | # state == 0 && ((contact == 2) && (wire3 == 0) && ((ts_power == 0) | (charger == 1))) |
|---|
| 567 | .names _na8 _nb4 _nb5 |
|---|
| 568 | .def 0 |
|---|
| 569 | 1 1 1 |
|---|
| 570 | .mv _nb6 2 lit unlit |
|---|
| 571 | .names _nb6 |
|---|
| 572 | lit |
|---|
| 573 | .mv _nb7 2 lit unlit |
|---|
| 574 | .names _nb7 |
|---|
| 575 | unlit |
|---|
| 576 | # state == 0 && ((contact == 2) && (wire3 == 0) && ((ts_power == 0) | (charger == 1))) ? 0 : 1 |
|---|
| 577 | .mv _nb8 2 lit unlit |
|---|
| 578 | .names _nb6 _nb7 _nb5 _nb8 |
|---|
| 579 | - - 0 =_nb7 |
|---|
| 580 | - - 1 =_nb6 |
|---|
| 581 | .mv _nb9 2 lit unlit |
|---|
| 582 | .names _nb9 |
|---|
| 583 | lit |
|---|
| 584 | # state == 2 ? 0 : state == 0 && ((contact == 2) && (wire3 == 0) && ((ts_power == 0) | (charger == 1))) ? 0 : 1 |
|---|
| 585 | .mv _nba 2 lit unlit |
|---|
| 586 | .names _nb9 _nb8 _na6 _nba |
|---|
| 587 | - - 0 =_nb8 |
|---|
| 588 | - - 1 =_nb9 |
|---|
| 589 | .mv _nbb 2 lit unlit |
|---|
| 590 | .names _nbb |
|---|
| 591 | unlit |
|---|
| 592 | # state == 1 ? 1 : state == 2 ? 0 : state == 0 && ((contact == 2) && (wire3 == 0) && ((ts_power == 0) | (charger == 1))) ? 0 : 1 |
|---|
| 593 | .mv _nbc 2 lit unlit |
|---|
| 594 | .names _nbb _nba _na4 _nbc |
|---|
| 595 | - - 0 =_nba |
|---|
| 596 | - - 1 =_nbb |
|---|
| 597 | .names _nbc lamp$raw_na3 |
|---|
| 598 | - =_nbc |
|---|
| 599 | .mv _nbe 3 good faulty1 faulty2 |
|---|
| 600 | .names _nbe |
|---|
| 601 | faulty1 |
|---|
| 602 | # state == 1 |
|---|
| 603 | .names state _nbe _nbd |
|---|
| 604 | .def 0 |
|---|
| 605 | - =state 1 |
|---|
| 606 | .names _nbd _nbf |
|---|
| 607 | - =_nbd |
|---|
| 608 | # state = 1 |
|---|
| 609 | .mv state$_nbd_nc0$true 3 good faulty1 faulty2 |
|---|
| 610 | .names state$_nbd_nc0$true |
|---|
| 611 | faulty1 |
|---|
| 612 | # if/else (state == 1) |
|---|
| 613 | .mv state$_nbd$raw_nc3 3 good faulty1 faulty2 |
|---|
| 614 | .names state$_nbd_nc0$true state _nbd state$_nbd$raw_nc3 |
|---|
| 615 | - - 0 =state |
|---|
| 616 | - - 1 =state$_nbd_nc0$true |
|---|
| 617 | .mv _nc5 3 good faulty1 faulty2 |
|---|
| 618 | .names _nc5 |
|---|
| 619 | faulty2 |
|---|
| 620 | # state == 2 |
|---|
| 621 | .names state$_nbd$raw_nc3 _nc5 _nc4 |
|---|
| 622 | .def 0 |
|---|
| 623 | - =state$_nbd$raw_nc3 1 |
|---|
| 624 | .names _nc4 _nc6 |
|---|
| 625 | - =_nc4 |
|---|
| 626 | # state = 2 |
|---|
| 627 | .mv state$_nc4_nc7$true 3 good faulty1 faulty2 |
|---|
| 628 | .names state$_nc4_nc7$true |
|---|
| 629 | faulty2 |
|---|
| 630 | # if/else (state == 2) |
|---|
| 631 | .mv state$_nc4$raw_nc8 3 good faulty1 faulty2 |
|---|
| 632 | .names state$_nc4_nc7$true state$_nbd$raw_nc3 _nc4 state$_nc4$raw_nc8 |
|---|
| 633 | - - 0 =state$_nbd$raw_nc3 |
|---|
| 634 | - - 1 =state$_nc4_nc7$true |
|---|
| 635 | .mv _ncd 3 good faulty1 faulty2 |
|---|
| 636 | .names _ncd |
|---|
| 637 | good |
|---|
| 638 | # state == 0 |
|---|
| 639 | .names state$_nc4$raw_nc8 _ncd _ncc |
|---|
| 640 | .def 0 |
|---|
| 641 | - =state$_nc4$raw_nc8 1 |
|---|
| 642 | .names _ncc _nce |
|---|
| 643 | - =_ncc |
|---|
| 644 | # state = r_state |
|---|
| 645 | .mv state$_ncc_ncf$true 3 good faulty1 faulty2 |
|---|
| 646 | .names r_state state$_ncc_ncf$true |
|---|
| 647 | - =r_state |
|---|
| 648 | # if/else (state == 0) |
|---|
| 649 | .mv state$_ncc$raw_nd0 3 good faulty1 faulty2 |
|---|
| 650 | .names state$_ncc_ncf$true state$_nc4$raw_nc8 _ncc state$_ncc$raw_nd0 |
|---|
| 651 | - - 0 =state$_nc4$raw_nc8 |
|---|
| 652 | - - 1 =state$_ncc_ncf$true |
|---|
| 653 | # conflict arbitrators |
|---|
| 654 | .names _nbf _nc6 _nce _nd4 |
|---|
| 655 | .def 0 |
|---|
| 656 | 1 - - 1 |
|---|
| 657 | - 1 - 1 |
|---|
| 658 | - - 1 1 |
|---|
| 659 | .mv _nd5 3 good faulty1 faulty2 |
|---|
| 660 | .names _nd4 state$_ncc$raw_nd0 state _nd5 |
|---|
| 661 | 1 - - =state$_ncc$raw_nd0 |
|---|
| 662 | 0 - - =state |
|---|
| 663 | .names lamp$raw_na3 lamp |
|---|
| 664 | - =lamp$raw_na3 |
|---|
| 665 | # non-blocking assignments |
|---|
| 666 | # latches |
|---|
| 667 | .r state$raw_na0 state |
|---|
| 668 | - =state$raw_na0 |
|---|
| 669 | .latch _nd5 state |
|---|
| 670 | # quasi-continuous assignment |
|---|
| 671 | .end |
|---|
| 672 | |
|---|
| 673 | |
|---|
| 674 | .model contact_mod |
|---|
| 675 | # I/O ports |
|---|
| 676 | .outputs contact |
|---|
| 677 | .inputs relay |
|---|
| 678 | |
|---|
| 679 | .mv r_state 3 good faulty1 faulty2 |
|---|
| 680 | .mv state 3 good faulty1 faulty2 |
|---|
| 681 | .mv contact 3 B middle C |
|---|
| 682 | .mv relay 2 pulling neutral |
|---|
| 683 | # state = 0 |
|---|
| 684 | .mv state$raw_nde 3 good faulty1 faulty2 |
|---|
| 685 | .names state$raw_nde |
|---|
| 686 | good |
|---|
| 687 | # non-blocking assignments for initial |
|---|
| 688 | # assign r_state = $NDset ( 0,1,2 ) |
|---|
| 689 | .names r_state |
|---|
| 690 | good |
|---|
| 691 | faulty1 |
|---|
| 692 | faulty2 |
|---|
| 693 | # assign contact = state == faulty1 ? 0 : state == faulty2 ? 2 : state == good && relay == pulling ? 2 : 0 |
|---|
| 694 | .mv contact$raw_ne1 3 B middle C |
|---|
| 695 | .mv _ne3 3 good faulty1 faulty2 |
|---|
| 696 | .names _ne3 |
|---|
| 697 | faulty1 |
|---|
| 698 | # state == 1 |
|---|
| 699 | .names state _ne3 _ne2 |
|---|
| 700 | .def 0 |
|---|
| 701 | - =state 1 |
|---|
| 702 | .mv _ne5 3 good faulty1 faulty2 |
|---|
| 703 | .names _ne5 |
|---|
| 704 | faulty2 |
|---|
| 705 | # state == 2 |
|---|
| 706 | .names state _ne5 _ne4 |
|---|
| 707 | .def 0 |
|---|
| 708 | - =state 1 |
|---|
| 709 | .mv _ne7 3 good faulty1 faulty2 |
|---|
| 710 | .names _ne7 |
|---|
| 711 | good |
|---|
| 712 | # state == 0 |
|---|
| 713 | .names state _ne7 _ne6 |
|---|
| 714 | .def 0 |
|---|
| 715 | - =state 1 |
|---|
| 716 | .mv _ne9 2 pulling neutral |
|---|
| 717 | .names _ne9 |
|---|
| 718 | pulling |
|---|
| 719 | # relay == 0 |
|---|
| 720 | .names relay _ne9 _ne8 |
|---|
| 721 | .def 0 |
|---|
| 722 | - =relay 1 |
|---|
| 723 | # state == 0 && relay == 0 |
|---|
| 724 | .names _ne6 _ne8 _nea |
|---|
| 725 | .def 0 |
|---|
| 726 | 1 1 1 |
|---|
| 727 | .mv _neb 3 B middle C |
|---|
| 728 | .names _neb |
|---|
| 729 | C |
|---|
| 730 | .mv _nec 3 B middle C |
|---|
| 731 | .names _nec |
|---|
| 732 | B |
|---|
| 733 | # state == 0 && relay == 0 ? 2 : 0 |
|---|
| 734 | .mv _ned 3 B middle C |
|---|
| 735 | .names _neb _nec _nea _ned |
|---|
| 736 | - - 0 =_nec |
|---|
| 737 | - - 1 =_neb |
|---|
| 738 | .mv _nee 3 B middle C |
|---|
| 739 | .names _nee |
|---|
| 740 | C |
|---|
| 741 | # state == 2 ? 2 : state == 0 && relay == 0 ? 2 : 0 |
|---|
| 742 | .mv _nef 3 B middle C |
|---|
| 743 | .names _nee _ned _ne4 _nef |
|---|
| 744 | - - 0 =_ned |
|---|
| 745 | - - 1 =_nee |
|---|
| 746 | .mv _nf0 3 B middle C |
|---|
| 747 | .names _nf0 |
|---|
| 748 | B |
|---|
| 749 | # state == 1 ? 0 : state == 2 ? 2 : state == 0 && relay == 0 ? 2 : 0 |
|---|
| 750 | .mv _nf1 3 B middle C |
|---|
| 751 | .names _nf0 _nef _ne2 _nf1 |
|---|
| 752 | - - 0 =_nef |
|---|
| 753 | - - 1 =_nf0 |
|---|
| 754 | .names _nf1 contact$raw_ne1 |
|---|
| 755 | - =_nf1 |
|---|
| 756 | .mv _nf3 3 good faulty1 faulty2 |
|---|
| 757 | .names _nf3 |
|---|
| 758 | faulty1 |
|---|
| 759 | # state == 1 |
|---|
| 760 | .names state _nf3 _nf2 |
|---|
| 761 | .def 0 |
|---|
| 762 | - =state 1 |
|---|
| 763 | .names _nf2 _nf4 |
|---|
| 764 | - =_nf2 |
|---|
| 765 | # state = 1 |
|---|
| 766 | .mv state$_nf2_nf5$true 3 good faulty1 faulty2 |
|---|
| 767 | .names state$_nf2_nf5$true |
|---|
| 768 | faulty1 |
|---|
| 769 | # if/else (state == 1) |
|---|
| 770 | .mv state$_nf2$raw_nf8 3 good faulty1 faulty2 |
|---|
| 771 | .names state$_nf2_nf5$true state _nf2 state$_nf2$raw_nf8 |
|---|
| 772 | - - 0 =state |
|---|
| 773 | - - 1 =state$_nf2_nf5$true |
|---|
| 774 | .mv _nfa 3 good faulty1 faulty2 |
|---|
| 775 | .names _nfa |
|---|
| 776 | faulty2 |
|---|
| 777 | # state == 2 |
|---|
| 778 | .names state$_nf2$raw_nf8 _nfa _nf9 |
|---|
| 779 | .def 0 |
|---|
| 780 | - =state$_nf2$raw_nf8 1 |
|---|
| 781 | .names _nf9 _nfb |
|---|
| 782 | - =_nf9 |
|---|
| 783 | # state = 2 |
|---|
| 784 | .mv state$_nf9_nfc$true 3 good faulty1 faulty2 |
|---|
| 785 | .names state$_nf9_nfc$true |
|---|
| 786 | faulty2 |
|---|
| 787 | # if/else (state == 2) |
|---|
| 788 | .mv state$_nf9$raw_nfd 3 good faulty1 faulty2 |
|---|
| 789 | .names state$_nf9_nfc$true state$_nf2$raw_nf8 _nf9 state$_nf9$raw_nfd |
|---|
| 790 | - - 0 =state$_nf2$raw_nf8 |
|---|
| 791 | - - 1 =state$_nf9_nfc$true |
|---|
| 792 | .mv _n102 3 good faulty1 faulty2 |
|---|
| 793 | .names _n102 |
|---|
| 794 | good |
|---|
| 795 | # state == 0 |
|---|
| 796 | .names state$_nf9$raw_nfd _n102 _n101 |
|---|
| 797 | .def 0 |
|---|
| 798 | - =state$_nf9$raw_nfd 1 |
|---|
| 799 | .names _n101 _n103 |
|---|
| 800 | - =_n101 |
|---|
| 801 | # state = r_state |
|---|
| 802 | .mv state$_n101_n104$true 3 good faulty1 faulty2 |
|---|
| 803 | .names r_state state$_n101_n104$true |
|---|
| 804 | - =r_state |
|---|
| 805 | # if/else (state == 0) |
|---|
| 806 | .mv state$_n101$raw_n105 3 good faulty1 faulty2 |
|---|
| 807 | .names state$_n101_n104$true state$_nf9$raw_nfd _n101 state$_n101$raw_n105 |
|---|
| 808 | - - 0 =state$_nf9$raw_nfd |
|---|
| 809 | - - 1 =state$_n101_n104$true |
|---|
| 810 | # conflict arbitrators |
|---|
| 811 | .names _nf4 _nfb _n103 _n109 |
|---|
| 812 | .def 0 |
|---|
| 813 | 1 - - 1 |
|---|
| 814 | - 1 - 1 |
|---|
| 815 | - - 1 1 |
|---|
| 816 | .mv _n10a 3 good faulty1 faulty2 |
|---|
| 817 | .names _n109 state$_n101$raw_n105 state _n10a |
|---|
| 818 | 1 - - =state$_n101$raw_n105 |
|---|
| 819 | 0 - - =state |
|---|
| 820 | .names contact$raw_ne1 contact |
|---|
| 821 | - =contact$raw_ne1 |
|---|
| 822 | # non-blocking assignments |
|---|
| 823 | # latches |
|---|
| 824 | .r state$raw_nde state |
|---|
| 825 | - =state$raw_nde |
|---|
| 826 | .latch _n10a state |
|---|
| 827 | # quasi-continuous assignment |
|---|
| 828 | .end |
|---|
| 829 | |
|---|
| 830 | |
|---|
| 831 | .model train_mod |
|---|
| 832 | # I/O ports |
|---|
| 833 | .outputs out |
|---|
| 834 | |
|---|
| 835 | .mv r9_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 836 | .mv r8_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 837 | .mv r6_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 838 | .mv r5_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 839 | .mv out 3 present1 present2 absent |
|---|
| 840 | .mv r10_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 841 | .mv r3_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 842 | .mv r2_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 843 | .mv r4_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 844 | .mv r1_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 845 | .mv train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 846 | .mv r7_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 847 | # train = 0 |
|---|
| 848 | .mv train$raw_n110 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 849 | .names train$raw_n110 |
|---|
| 850 | t1 |
|---|
| 851 | # non-blocking assignments for initial |
|---|
| 852 | # assign r1_train = $NDset ( 0,1 ) |
|---|
| 853 | .names r1_train |
|---|
| 854 | t1 |
|---|
| 855 | t2 |
|---|
| 856 | # assign r2_train = $NDset ( 1,2 ) |
|---|
| 857 | .names r2_train |
|---|
| 858 | t2 |
|---|
| 859 | t3 |
|---|
| 860 | # assign r3_train = $NDset ( 2,3 ) |
|---|
| 861 | .names r3_train |
|---|
| 862 | t3 |
|---|
| 863 | t4 |
|---|
| 864 | # assign r4_train = $NDset ( 3,4 ) |
|---|
| 865 | .names r4_train |
|---|
| 866 | t4 |
|---|
| 867 | t5 |
|---|
| 868 | # assign r5_train = $NDset ( 4,5 ) |
|---|
| 869 | .names r5_train |
|---|
| 870 | t5 |
|---|
| 871 | t6 |
|---|
| 872 | # assign r6_train = $NDset ( 5,6 ) |
|---|
| 873 | .names r6_train |
|---|
| 874 | t6 |
|---|
| 875 | t7 |
|---|
| 876 | # assign r7_train = $NDset ( 6,7 ) |
|---|
| 877 | .names r7_train |
|---|
| 878 | t7 |
|---|
| 879 | t8 |
|---|
| 880 | # assign r8_train = $NDset ( 7,8 ) |
|---|
| 881 | .names r8_train |
|---|
| 882 | t8 |
|---|
| 883 | t9 |
|---|
| 884 | # assign r9_train = $NDset ( 8,9 ) |
|---|
| 885 | .names r9_train |
|---|
| 886 | t9 |
|---|
| 887 | t10 |
|---|
| 888 | # assign r10_train = $NDset ( 9,0 ) |
|---|
| 889 | .names r10_train |
|---|
| 890 | t10 |
|---|
| 891 | t1 |
|---|
| 892 | # assign out = (train == t1 ) ? 2 : 0 |
|---|
| 893 | .mv out$raw_n125 3 present1 present2 absent |
|---|
| 894 | .mv _n127 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 895 | .names _n127 |
|---|
| 896 | t1 |
|---|
| 897 | # train == 0 |
|---|
| 898 | .names train _n127 _n126 |
|---|
| 899 | .def 0 |
|---|
| 900 | - =train 1 |
|---|
| 901 | .mv _n128 3 present1 present2 absent |
|---|
| 902 | .names _n128 |
|---|
| 903 | absent |
|---|
| 904 | .mv _n129 3 present1 present2 absent |
|---|
| 905 | .names _n129 |
|---|
| 906 | present1 |
|---|
| 907 | # (train == 0) ? 2 : 0 |
|---|
| 908 | .mv _n12a 3 present1 present2 absent |
|---|
| 909 | .names _n128 _n129 _n126 _n12a |
|---|
| 910 | - - 0 =_n129 |
|---|
| 911 | - - 1 =_n128 |
|---|
| 912 | .names _n12a out$raw_n125 |
|---|
| 913 | - =_n12a |
|---|
| 914 | .mv _n12d 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 915 | .names _n12d |
|---|
| 916 | t1 |
|---|
| 917 | .names train _n12d _n12c |
|---|
| 918 | .def 0 |
|---|
| 919 | - =train 1 |
|---|
| 920 | .names _n12c _n12b |
|---|
| 921 | 1 1 |
|---|
| 922 | 0 0 |
|---|
| 923 | # train = r1_train |
|---|
| 924 | .mv train$_n12b_n12e$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 925 | .names r1_train train$_n12b_n12e$true |
|---|
| 926 | - =r1_train |
|---|
| 927 | .mv _n131 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 928 | .names _n131 |
|---|
| 929 | t2 |
|---|
| 930 | .names train _n131 _n130 |
|---|
| 931 | .def 0 |
|---|
| 932 | - =train 1 |
|---|
| 933 | .names _n130 _n12f |
|---|
| 934 | 1 1 |
|---|
| 935 | 0 0 |
|---|
| 936 | # train = r2_train |
|---|
| 937 | .mv train$_n12f_n132$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 938 | .names r2_train train$_n12f_n132$true |
|---|
| 939 | - =r2_train |
|---|
| 940 | .mv _n135 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 941 | .names _n135 |
|---|
| 942 | t3 |
|---|
| 943 | .names train _n135 _n134 |
|---|
| 944 | .def 0 |
|---|
| 945 | - =train 1 |
|---|
| 946 | .names _n134 _n133 |
|---|
| 947 | 1 1 |
|---|
| 948 | 0 0 |
|---|
| 949 | # train = r3_train |
|---|
| 950 | .mv train$_n133_n136$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 951 | .names r3_train train$_n133_n136$true |
|---|
| 952 | - =r3_train |
|---|
| 953 | .mv _n139 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 954 | .names _n139 |
|---|
| 955 | t4 |
|---|
| 956 | .names train _n139 _n138 |
|---|
| 957 | .def 0 |
|---|
| 958 | - =train 1 |
|---|
| 959 | .names _n138 _n137 |
|---|
| 960 | 1 1 |
|---|
| 961 | 0 0 |
|---|
| 962 | # train = r4_train |
|---|
| 963 | .mv train$_n137_n13a$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 964 | .names r4_train train$_n137_n13a$true |
|---|
| 965 | - =r4_train |
|---|
| 966 | .mv _n13d 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 967 | .names _n13d |
|---|
| 968 | t5 |
|---|
| 969 | .names train _n13d _n13c |
|---|
| 970 | .def 0 |
|---|
| 971 | - =train 1 |
|---|
| 972 | .names _n13c _n13b |
|---|
| 973 | 1 1 |
|---|
| 974 | 0 0 |
|---|
| 975 | # train = r5_train |
|---|
| 976 | .mv train$_n13b_n13e$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 977 | .names r5_train train$_n13b_n13e$true |
|---|
| 978 | - =r5_train |
|---|
| 979 | .mv _n141 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 980 | .names _n141 |
|---|
| 981 | t6 |
|---|
| 982 | .names train _n141 _n140 |
|---|
| 983 | .def 0 |
|---|
| 984 | - =train 1 |
|---|
| 985 | .names _n140 _n13f |
|---|
| 986 | 1 1 |
|---|
| 987 | 0 0 |
|---|
| 988 | # train = r6_train |
|---|
| 989 | .mv train$_n13f_n142$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 990 | .names r6_train train$_n13f_n142$true |
|---|
| 991 | - =r6_train |
|---|
| 992 | .mv _n145 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 993 | .names _n145 |
|---|
| 994 | t7 |
|---|
| 995 | .names train _n145 _n144 |
|---|
| 996 | .def 0 |
|---|
| 997 | - =train 1 |
|---|
| 998 | .names _n144 _n143 |
|---|
| 999 | 1 1 |
|---|
| 1000 | 0 0 |
|---|
| 1001 | # train = r7_train |
|---|
| 1002 | .mv train$_n143_n146$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1003 | .names r7_train train$_n143_n146$true |
|---|
| 1004 | - =r7_train |
|---|
| 1005 | .mv _n149 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1006 | .names _n149 |
|---|
| 1007 | t8 |
|---|
| 1008 | .names train _n149 _n148 |
|---|
| 1009 | .def 0 |
|---|
| 1010 | - =train 1 |
|---|
| 1011 | .names _n148 _n147 |
|---|
| 1012 | 1 1 |
|---|
| 1013 | 0 0 |
|---|
| 1014 | # train = r8_train |
|---|
| 1015 | .mv train$_n147_n14a$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1016 | .names r8_train train$_n147_n14a$true |
|---|
| 1017 | - =r8_train |
|---|
| 1018 | .mv _n14d 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1019 | .names _n14d |
|---|
| 1020 | t9 |
|---|
| 1021 | .names train _n14d _n14c |
|---|
| 1022 | .def 0 |
|---|
| 1023 | - =train 1 |
|---|
| 1024 | .names _n14c _n14b |
|---|
| 1025 | 1 1 |
|---|
| 1026 | 0 0 |
|---|
| 1027 | # train = r9_train |
|---|
| 1028 | .mv train$_n14b_n14e$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1029 | .names r9_train train$_n14b_n14e$true |
|---|
| 1030 | - =r9_train |
|---|
| 1031 | .mv _n151 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1032 | .names _n151 |
|---|
| 1033 | t10 |
|---|
| 1034 | .names train _n151 _n150 |
|---|
| 1035 | .def 0 |
|---|
| 1036 | - =train 1 |
|---|
| 1037 | .names _n150 _n14f |
|---|
| 1038 | 1 1 |
|---|
| 1039 | 0 0 |
|---|
| 1040 | # train = r10_train |
|---|
| 1041 | .mv train$_n14f_n152$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1042 | .names r10_train train$_n14f_n152$true |
|---|
| 1043 | - =r10_train |
|---|
| 1044 | # case (train ) |
|---|
| 1045 | .mv train$_n14f$raw_n155 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1046 | .names train$_n14f_n152$true train _n14f train$_n14f$raw_n155 |
|---|
| 1047 | - - 0 =train |
|---|
| 1048 | - - 1 =train$_n14f_n152$true |
|---|
| 1049 | .mv train$_n14b$raw_n156 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1050 | .names train$_n14b_n14e$true train$_n14f$raw_n155 _n14b train$_n14b$raw_n156 |
|---|
| 1051 | - - 0 =train$_n14f$raw_n155 |
|---|
| 1052 | - - 1 =train$_n14b_n14e$true |
|---|
| 1053 | .mv train$_n147$raw_n15a 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1054 | .names train$_n147_n14a$true train$_n14b$raw_n156 _n147 train$_n147$raw_n15a |
|---|
| 1055 | - - 0 =train$_n14b$raw_n156 |
|---|
| 1056 | - - 1 =train$_n147_n14a$true |
|---|
| 1057 | .mv train$_n143$raw_n15e 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1058 | .names train$_n143_n146$true train$_n147$raw_n15a _n143 train$_n143$raw_n15e |
|---|
| 1059 | - - 0 =train$_n147$raw_n15a |
|---|
| 1060 | - - 1 =train$_n143_n146$true |
|---|
| 1061 | .mv train$_n13f$raw_n162 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1062 | .names train$_n13f_n142$true train$_n143$raw_n15e _n13f train$_n13f$raw_n162 |
|---|
| 1063 | - - 0 =train$_n143$raw_n15e |
|---|
| 1064 | - - 1 =train$_n13f_n142$true |
|---|
| 1065 | .mv train$_n13b$raw_n166 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1066 | .names train$_n13b_n13e$true train$_n13f$raw_n162 _n13b train$_n13b$raw_n166 |
|---|
| 1067 | - - 0 =train$_n13f$raw_n162 |
|---|
| 1068 | - - 1 =train$_n13b_n13e$true |
|---|
| 1069 | .mv train$_n137$raw_n16a 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1070 | .names train$_n137_n13a$true train$_n13b$raw_n166 _n137 train$_n137$raw_n16a |
|---|
| 1071 | - - 0 =train$_n13b$raw_n166 |
|---|
| 1072 | - - 1 =train$_n137_n13a$true |
|---|
| 1073 | .mv train$_n133$raw_n16e 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1074 | .names train$_n133_n136$true train$_n137$raw_n16a _n133 train$_n133$raw_n16e |
|---|
| 1075 | - - 0 =train$_n137$raw_n16a |
|---|
| 1076 | - - 1 =train$_n133_n136$true |
|---|
| 1077 | .mv train$_n12f$raw_n172 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1078 | .names train$_n12f_n132$true train$_n133$raw_n16e _n12f train$_n12f$raw_n172 |
|---|
| 1079 | - - 0 =train$_n133$raw_n16e |
|---|
| 1080 | - - 1 =train$_n12f_n132$true |
|---|
| 1081 | .mv train$_n12b$raw_n176 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1082 | .names train$_n12b_n12e$true train$_n12f$raw_n172 _n12b train$_n12b$raw_n176 |
|---|
| 1083 | - - 0 =train$_n12f$raw_n172 |
|---|
| 1084 | - - 1 =train$_n12b_n12e$true |
|---|
| 1085 | # conflict arbitrators |
|---|
| 1086 | .names out$raw_n125 out |
|---|
| 1087 | - =out$raw_n125 |
|---|
| 1088 | .names _n12b _n12f _n133 _n137 _n13b _n13f _n143 _n147 _n14b _n14f _n17a |
|---|
| 1089 | .def 0 |
|---|
| 1090 | 1 - - - - - - - - - 1 |
|---|
| 1091 | 0 1 - - - - - - - - 1 |
|---|
| 1092 | 0 0 1 - - - - - - - 1 |
|---|
| 1093 | 0 0 0 1 - - - - - - 1 |
|---|
| 1094 | 0 0 0 0 1 - - - - - 1 |
|---|
| 1095 | 0 0 0 0 0 1 - - - - 1 |
|---|
| 1096 | 0 0 0 0 0 0 1 - - - 1 |
|---|
| 1097 | 0 0 0 0 0 0 0 1 - - 1 |
|---|
| 1098 | 0 0 0 0 0 0 0 0 1 - 1 |
|---|
| 1099 | 0 0 0 0 0 0 0 0 0 1 1 |
|---|
| 1100 | .mv _n17b 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 |
|---|
| 1101 | .names _n17a train$_n12b$raw_n176 train _n17b |
|---|
| 1102 | 1 - - =train$_n12b$raw_n176 |
|---|
| 1103 | 0 - - =train |
|---|
| 1104 | # non-blocking assignments |
|---|
| 1105 | # latches |
|---|
| 1106 | .r train$raw_n110 train |
|---|
| 1107 | - =train$raw_n110 |
|---|
| 1108 | .latch _n17b train |
|---|
| 1109 | # quasi-continuous assignment |
|---|
| 1110 | .end |
|---|
| 1111 | |
|---|
| 1112 | |
|---|
| 1113 | .model track_system_mod |
|---|
| 1114 | # I/O ports |
|---|
| 1115 | .inputs wire1 |
|---|
| 1116 | .inputs wire2 |
|---|
| 1117 | .outputs ts_power |
|---|
| 1118 | .inputs train |
|---|
| 1119 | .inputs contact |
|---|
| 1120 | |
|---|
| 1121 | .mv wire1 2 conduct open |
|---|
| 1122 | .mv wire2 2 conduct open |
|---|
| 1123 | .mv r_state 3 good faulty1 faulty2 |
|---|
| 1124 | .mv state 3 good faulty1 faulty2 |
|---|
| 1125 | .mv ts_power 2 on off |
|---|
| 1126 | .mv train 3 present1 present2 absent |
|---|
| 1127 | .mv contact 3 B middle C |
|---|
| 1128 | # state = 0 |
|---|
| 1129 | .mv state$raw_n192 3 good faulty1 faulty2 |
|---|
| 1130 | .names state$raw_n192 |
|---|
| 1131 | good |
|---|
| 1132 | # non-blocking assignments for initial |
|---|
| 1133 | # assign r_state = $NDset ( 0,1,2 ) |
|---|
| 1134 | .names r_state |
|---|
| 1135 | good |
|---|
| 1136 | faulty1 |
|---|
| 1137 | faulty2 |
|---|
| 1138 | # assign ts_power = state == faulty1 ? 0 : state == faulty2 ? 1 : state == good && ((wire1 == conduct ) && (wire2 == conduct ) && ((train != absent ) | (contact == B ))) ? 0 : 1 |
|---|
| 1139 | .mv ts_power$raw_n195 2 on off |
|---|
| 1140 | .mv _n197 3 good faulty1 faulty2 |
|---|
| 1141 | .names _n197 |
|---|
| 1142 | faulty1 |
|---|
| 1143 | # state == 1 |
|---|
| 1144 | .names state _n197 _n196 |
|---|
| 1145 | .def 0 |
|---|
| 1146 | - =state 1 |
|---|
| 1147 | .mv _n199 3 good faulty1 faulty2 |
|---|
| 1148 | .names _n199 |
|---|
| 1149 | faulty2 |
|---|
| 1150 | # state == 2 |
|---|
| 1151 | .names state _n199 _n198 |
|---|
| 1152 | .def 0 |
|---|
| 1153 | - =state 1 |
|---|
| 1154 | .mv _n19b 3 good faulty1 faulty2 |
|---|
| 1155 | .names _n19b |
|---|
| 1156 | good |
|---|
| 1157 | # state == 0 |
|---|
| 1158 | .names state _n19b _n19a |
|---|
| 1159 | .def 0 |
|---|
| 1160 | - =state 1 |
|---|
| 1161 | .mv _n19d 2 conduct open |
|---|
| 1162 | .names _n19d |
|---|
| 1163 | conduct |
|---|
| 1164 | # wire1 == 0 |
|---|
| 1165 | .names wire1 _n19d _n19c |
|---|
| 1166 | .def 0 |
|---|
| 1167 | - =wire1 1 |
|---|
| 1168 | .mv _n19f 2 conduct open |
|---|
| 1169 | .names _n19f |
|---|
| 1170 | conduct |
|---|
| 1171 | # wire2 == 0 |
|---|
| 1172 | .names wire2 _n19f _n19e |
|---|
| 1173 | .def 0 |
|---|
| 1174 | - =wire2 1 |
|---|
| 1175 | # (wire1 == 0) && (wire2 == 0) |
|---|
| 1176 | .names _n19c _n19e _n1a0 |
|---|
| 1177 | .def 0 |
|---|
| 1178 | 1 1 1 |
|---|
| 1179 | .mv _n1a2 3 present1 present2 absent |
|---|
| 1180 | .names _n1a2 |
|---|
| 1181 | absent |
|---|
| 1182 | # train != 2 |
|---|
| 1183 | .names train _n1a2 _n1a1 |
|---|
| 1184 | .def 1 |
|---|
| 1185 | - =train 0 |
|---|
| 1186 | .mv _n1a4 3 B middle C |
|---|
| 1187 | .names _n1a4 |
|---|
| 1188 | B |
|---|
| 1189 | # contact == 0 |
|---|
| 1190 | .names contact _n1a4 _n1a3 |
|---|
| 1191 | .def 0 |
|---|
| 1192 | - =contact 1 |
|---|
| 1193 | # (train != 2) | (contact == 0) |
|---|
| 1194 | .names _n1a1 _n1a3 _n1a5 |
|---|
| 1195 | .def 1 |
|---|
| 1196 | 0 0 0 |
|---|
| 1197 | # (wire1 == 0) && (wire2 == 0) && ((train != 2) | (contact == 0)) |
|---|
| 1198 | .names _n1a0 _n1a5 _n1a6 |
|---|
| 1199 | .def 0 |
|---|
| 1200 | 1 1 1 |
|---|
| 1201 | # state == 0 && ((wire1 == 0) && (wire2 == 0) && ((train != 2) | (contact == 0))) |
|---|
| 1202 | .names _n19a _n1a6 _n1a7 |
|---|
| 1203 | .def 0 |
|---|
| 1204 | 1 1 1 |
|---|
| 1205 | .mv _n1a8 2 on off |
|---|
| 1206 | .names _n1a8 |
|---|
| 1207 | on |
|---|
| 1208 | .mv _n1a9 2 on off |
|---|
| 1209 | .names _n1a9 |
|---|
| 1210 | off |
|---|
| 1211 | # state == 0 && ((wire1 == 0) && (wire2 == 0) && ((train != 2) | (contact == 0))) ? 0 : 1 |
|---|
| 1212 | .mv _n1aa 2 on off |
|---|
| 1213 | .names _n1a8 _n1a9 _n1a7 _n1aa |
|---|
| 1214 | - - 0 =_n1a9 |
|---|
| 1215 | - - 1 =_n1a8 |
|---|
| 1216 | .mv _n1ab 2 on off |
|---|
| 1217 | .names _n1ab |
|---|
| 1218 | off |
|---|
| 1219 | # state == 2 ? 1 : state == 0 && ((wire1 == 0) && (wire2 == 0) && ((train != 2) | (contact == 0))) ? 0 : 1 |
|---|
| 1220 | .mv _n1ac 2 on off |
|---|
| 1221 | .names _n1ab _n1aa _n198 _n1ac |
|---|
| 1222 | - - 0 =_n1aa |
|---|
| 1223 | - - 1 =_n1ab |
|---|
| 1224 | .mv _n1ad 2 on off |
|---|
| 1225 | .names _n1ad |
|---|
| 1226 | on |
|---|
| 1227 | # state == 1 ? 0 : state == 2 ? 1 : state == 0 && ((wire1 == 0) && (wire2 == 0) && ((train != 2) | (contact == 0))) ? 0 : 1 |
|---|
| 1228 | .mv _n1ae 2 on off |
|---|
| 1229 | .names _n1ad _n1ac _n196 _n1ae |
|---|
| 1230 | - - 0 =_n1ac |
|---|
| 1231 | - - 1 =_n1ad |
|---|
| 1232 | .names _n1ae ts_power$raw_n195 |
|---|
| 1233 | - =_n1ae |
|---|
| 1234 | .mv _n1b0 3 good faulty1 faulty2 |
|---|
| 1235 | .names _n1b0 |
|---|
| 1236 | faulty1 |
|---|
| 1237 | # state == 1 |
|---|
| 1238 | .names state _n1b0 _n1af |
|---|
| 1239 | .def 0 |
|---|
| 1240 | - =state 1 |
|---|
| 1241 | .names _n1af _n1b1 |
|---|
| 1242 | - =_n1af |
|---|
| 1243 | # state = 1 |
|---|
| 1244 | .mv state$_n1af_n1b2$true 3 good faulty1 faulty2 |
|---|
| 1245 | .names state$_n1af_n1b2$true |
|---|
| 1246 | faulty1 |
|---|
| 1247 | # if/else (state == 1) |
|---|
| 1248 | .mv state$_n1af$raw_n1b5 3 good faulty1 faulty2 |
|---|
| 1249 | .names state$_n1af_n1b2$true state _n1af state$_n1af$raw_n1b5 |
|---|
| 1250 | - - 0 =state |
|---|
| 1251 | - - 1 =state$_n1af_n1b2$true |
|---|
| 1252 | .mv _n1b7 3 good faulty1 faulty2 |
|---|
| 1253 | .names _n1b7 |
|---|
| 1254 | faulty2 |
|---|
| 1255 | # state == 2 |
|---|
| 1256 | .names state$_n1af$raw_n1b5 _n1b7 _n1b6 |
|---|
| 1257 | .def 0 |
|---|
| 1258 | - =state$_n1af$raw_n1b5 1 |
|---|
| 1259 | .names _n1b6 _n1b8 |
|---|
| 1260 | - =_n1b6 |
|---|
| 1261 | # state = 2 |
|---|
| 1262 | .mv state$_n1b6_n1b9$true 3 good faulty1 faulty2 |
|---|
| 1263 | .names state$_n1b6_n1b9$true |
|---|
| 1264 | faulty2 |
|---|
| 1265 | # if/else (state == 2) |
|---|
| 1266 | .mv state$_n1b6$raw_n1ba 3 good faulty1 faulty2 |
|---|
| 1267 | .names state$_n1b6_n1b9$true state$_n1af$raw_n1b5 _n1b6 state$_n1b6$raw_n1ba |
|---|
| 1268 | - - 0 =state$_n1af$raw_n1b5 |
|---|
| 1269 | - - 1 =state$_n1b6_n1b9$true |
|---|
| 1270 | .mv _n1bf 3 good faulty1 faulty2 |
|---|
| 1271 | .names _n1bf |
|---|
| 1272 | good |
|---|
| 1273 | # state == 0 |
|---|
| 1274 | .names state$_n1b6$raw_n1ba _n1bf _n1be |
|---|
| 1275 | .def 0 |
|---|
| 1276 | - =state$_n1b6$raw_n1ba 1 |
|---|
| 1277 | .names _n1be _n1c0 |
|---|
| 1278 | - =_n1be |
|---|
| 1279 | # state = r_state |
|---|
| 1280 | .mv state$_n1be_n1c1$true 3 good faulty1 faulty2 |
|---|
| 1281 | .names r_state state$_n1be_n1c1$true |
|---|
| 1282 | - =r_state |
|---|
| 1283 | # if/else (state == 0) |
|---|
| 1284 | .mv state$_n1be$raw_n1c2 3 good faulty1 faulty2 |
|---|
| 1285 | .names state$_n1be_n1c1$true state$_n1b6$raw_n1ba _n1be state$_n1be$raw_n1c2 |
|---|
| 1286 | - - 0 =state$_n1b6$raw_n1ba |
|---|
| 1287 | - - 1 =state$_n1be_n1c1$true |
|---|
| 1288 | # conflict arbitrators |
|---|
| 1289 | .names _n1b1 _n1b8 _n1c0 _n1c6 |
|---|
| 1290 | .def 0 |
|---|
| 1291 | 1 - - 1 |
|---|
| 1292 | - 1 - 1 |
|---|
| 1293 | - - 1 1 |
|---|
| 1294 | .mv _n1c7 3 good faulty1 faulty2 |
|---|
| 1295 | .names _n1c6 state$_n1be$raw_n1c2 state _n1c7 |
|---|
| 1296 | 1 - - =state$_n1be$raw_n1c2 |
|---|
| 1297 | 0 - - =state |
|---|
| 1298 | .names ts_power$raw_n195 ts_power |
|---|
| 1299 | - =ts_power$raw_n195 |
|---|
| 1300 | # non-blocking assignments |
|---|
| 1301 | # latches |
|---|
| 1302 | .r state$raw_n192 state |
|---|
| 1303 | - =state$raw_n192 |
|---|
| 1304 | .latch _n1c7 state |
|---|
| 1305 | # quasi-continuous assignment |
|---|
| 1306 | .end |
|---|
| 1307 | |
|---|
| 1308 | |
|---|
| 1309 | .model interpretation_mod |
|---|
| 1310 | # I/O ports |
|---|
| 1311 | .outputs out |
|---|
| 1312 | .inputs lamp |
|---|
| 1313 | |
|---|
| 1314 | .mv out 2 go stop |
|---|
| 1315 | .mv state 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1316 | .mv lamp 2 lit unlit |
|---|
| 1317 | # state = 0 |
|---|
| 1318 | .mv state$raw_n1cf 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1319 | .names state$raw_n1cf |
|---|
| 1320 | stop1 |
|---|
| 1321 | # non-blocking assignments for initial |
|---|
| 1322 | # assign out = state == go3 | state == go4 ? 0 : 1 |
|---|
| 1323 | .mv out$raw_n1d0 2 go stop |
|---|
| 1324 | .mv _n1d2 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1325 | .names _n1d2 |
|---|
| 1326 | go3 |
|---|
| 1327 | # state == 4 |
|---|
| 1328 | .names state _n1d2 _n1d1 |
|---|
| 1329 | .def 0 |
|---|
| 1330 | - =state 1 |
|---|
| 1331 | .mv _n1d4 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1332 | .names _n1d4 |
|---|
| 1333 | go4 |
|---|
| 1334 | # state == 5 |
|---|
| 1335 | .names state _n1d4 _n1d3 |
|---|
| 1336 | .def 0 |
|---|
| 1337 | - =state 1 |
|---|
| 1338 | # state == 4 | state == 5 |
|---|
| 1339 | .names _n1d1 _n1d3 _n1d5 |
|---|
| 1340 | .def 1 |
|---|
| 1341 | 0 0 0 |
|---|
| 1342 | .mv _n1d6 2 go stop |
|---|
| 1343 | .names _n1d6 |
|---|
| 1344 | go |
|---|
| 1345 | .mv _n1d7 2 go stop |
|---|
| 1346 | .names _n1d7 |
|---|
| 1347 | stop |
|---|
| 1348 | # state == 4 | state == 5 ? 0 : 1 |
|---|
| 1349 | .mv _n1d8 2 go stop |
|---|
| 1350 | .names _n1d6 _n1d7 _n1d5 _n1d8 |
|---|
| 1351 | - - 0 =_n1d7 |
|---|
| 1352 | - - 1 =_n1d6 |
|---|
| 1353 | .names _n1d8 out$raw_n1d0 |
|---|
| 1354 | - =_n1d8 |
|---|
| 1355 | .mv _n1db 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1356 | .names _n1db |
|---|
| 1357 | stop1 |
|---|
| 1358 | .names state _n1db _n1da |
|---|
| 1359 | .def 0 |
|---|
| 1360 | - =state 1 |
|---|
| 1361 | .names _n1da _n1d9 |
|---|
| 1362 | 1 1 |
|---|
| 1363 | 0 0 |
|---|
| 1364 | .mv _n1dd 2 lit unlit |
|---|
| 1365 | .names _n1dd |
|---|
| 1366 | lit |
|---|
| 1367 | # lamp == 0 |
|---|
| 1368 | .names lamp _n1dd _n1dc |
|---|
| 1369 | .def 0 |
|---|
| 1370 | - =lamp 1 |
|---|
| 1371 | .names _n1dc _n1de |
|---|
| 1372 | - =_n1dc |
|---|
| 1373 | # state = 1 |
|---|
| 1374 | .mv state$_n1dc_n1df$true 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1375 | .names state$_n1dc_n1df$true |
|---|
| 1376 | stop2 |
|---|
| 1377 | # state = 0 |
|---|
| 1378 | .mv state$_n1dc_n1e0$false 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1379 | .names state$_n1dc_n1e0$false |
|---|
| 1380 | stop1 |
|---|
| 1381 | # if/else (lamp == 0) |
|---|
| 1382 | .mv state$_n1dc$raw_n1e2 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1383 | .names state$_n1dc_n1df$true state$_n1dc_n1e0$false _n1dc state$_n1dc$raw_n1e2 |
|---|
| 1384 | - - 0 =state$_n1dc_n1e0$false |
|---|
| 1385 | - - 1 =state$_n1dc_n1df$true |
|---|
| 1386 | .mv _n1e7 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1387 | .names _n1e7 |
|---|
| 1388 | stop2 |
|---|
| 1389 | .names state _n1e7 _n1e6 |
|---|
| 1390 | .def 0 |
|---|
| 1391 | - =state 1 |
|---|
| 1392 | .names _n1e6 _n1e5 |
|---|
| 1393 | 1 1 |
|---|
| 1394 | 0 0 |
|---|
| 1395 | .mv _n1e9 2 lit unlit |
|---|
| 1396 | .names _n1e9 |
|---|
| 1397 | unlit |
|---|
| 1398 | # lamp == 1 |
|---|
| 1399 | .names lamp _n1e9 _n1e8 |
|---|
| 1400 | .def 0 |
|---|
| 1401 | - =lamp 1 |
|---|
| 1402 | .names _n1e8 _n1ea |
|---|
| 1403 | - =_n1e8 |
|---|
| 1404 | # state = 2 |
|---|
| 1405 | .mv state$_n1e8_n1eb$true 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1406 | .names state$_n1e8_n1eb$true |
|---|
| 1407 | go1 |
|---|
| 1408 | # state = 0 |
|---|
| 1409 | .mv state$_n1e8_n1ec$false 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1410 | .names state$_n1e8_n1ec$false |
|---|
| 1411 | stop1 |
|---|
| 1412 | # if/else (lamp == 1) |
|---|
| 1413 | .mv state$_n1e8$raw_n1ee 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1414 | .names state$_n1e8_n1eb$true state$_n1e8_n1ec$false _n1e8 state$_n1e8$raw_n1ee |
|---|
| 1415 | - - 0 =state$_n1e8_n1ec$false |
|---|
| 1416 | - - 1 =state$_n1e8_n1eb$true |
|---|
| 1417 | .mv _n1f3 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1418 | .names _n1f3 |
|---|
| 1419 | go1 |
|---|
| 1420 | .names state _n1f3 _n1f2 |
|---|
| 1421 | .def 0 |
|---|
| 1422 | - =state 1 |
|---|
| 1423 | .names _n1f2 _n1f1 |
|---|
| 1424 | 1 1 |
|---|
| 1425 | 0 0 |
|---|
| 1426 | .mv _n1f5 2 lit unlit |
|---|
| 1427 | .names _n1f5 |
|---|
| 1428 | lit |
|---|
| 1429 | # lamp == 0 |
|---|
| 1430 | .names lamp _n1f5 _n1f4 |
|---|
| 1431 | .def 0 |
|---|
| 1432 | - =lamp 1 |
|---|
| 1433 | .names _n1f4 _n1f6 |
|---|
| 1434 | - =_n1f4 |
|---|
| 1435 | # state = 3 |
|---|
| 1436 | .mv state$_n1f4_n1f7$true 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1437 | .names state$_n1f4_n1f7$true |
|---|
| 1438 | go2 |
|---|
| 1439 | # state = 0 |
|---|
| 1440 | .mv state$_n1f4_n1f8$false 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1441 | .names state$_n1f4_n1f8$false |
|---|
| 1442 | stop1 |
|---|
| 1443 | # if/else (lamp == 0) |
|---|
| 1444 | .mv state$_n1f4$raw_n1fa 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1445 | .names state$_n1f4_n1f7$true state$_n1f4_n1f8$false _n1f4 state$_n1f4$raw_n1fa |
|---|
| 1446 | - - 0 =state$_n1f4_n1f8$false |
|---|
| 1447 | - - 1 =state$_n1f4_n1f7$true |
|---|
| 1448 | .mv _n1ff 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1449 | .names _n1ff |
|---|
| 1450 | go2 |
|---|
| 1451 | .names state _n1ff _n1fe |
|---|
| 1452 | .def 0 |
|---|
| 1453 | - =state 1 |
|---|
| 1454 | .names _n1fe _n1fd |
|---|
| 1455 | 1 1 |
|---|
| 1456 | 0 0 |
|---|
| 1457 | .mv _n201 2 lit unlit |
|---|
| 1458 | .names _n201 |
|---|
| 1459 | unlit |
|---|
| 1460 | # lamp == 1 |
|---|
| 1461 | .names lamp _n201 _n200 |
|---|
| 1462 | .def 0 |
|---|
| 1463 | - =lamp 1 |
|---|
| 1464 | .names _n200 _n202 |
|---|
| 1465 | - =_n200 |
|---|
| 1466 | # state = 4 |
|---|
| 1467 | .mv state$_n200_n203$true 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1468 | .names state$_n200_n203$true |
|---|
| 1469 | go3 |
|---|
| 1470 | # state = 0 |
|---|
| 1471 | .mv state$_n200_n204$false 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1472 | .names state$_n200_n204$false |
|---|
| 1473 | stop1 |
|---|
| 1474 | # if/else (lamp == 1) |
|---|
| 1475 | .mv state$_n200$raw_n206 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1476 | .names state$_n200_n203$true state$_n200_n204$false _n200 state$_n200$raw_n206 |
|---|
| 1477 | - - 0 =state$_n200_n204$false |
|---|
| 1478 | - - 1 =state$_n200_n203$true |
|---|
| 1479 | .mv _n20b 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1480 | .names _n20b |
|---|
| 1481 | go3 |
|---|
| 1482 | .names state _n20b _n20a |
|---|
| 1483 | .def 0 |
|---|
| 1484 | - =state 1 |
|---|
| 1485 | .names _n20a _n209 |
|---|
| 1486 | 1 1 |
|---|
| 1487 | 0 0 |
|---|
| 1488 | .mv _n20d 2 lit unlit |
|---|
| 1489 | .names _n20d |
|---|
| 1490 | lit |
|---|
| 1491 | # lamp == 0 |
|---|
| 1492 | .names lamp _n20d _n20c |
|---|
| 1493 | .def 0 |
|---|
| 1494 | - =lamp 1 |
|---|
| 1495 | .names _n20c _n20e |
|---|
| 1496 | - =_n20c |
|---|
| 1497 | # state = 5 |
|---|
| 1498 | .mv state$_n20c_n20f$true 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1499 | .names state$_n20c_n20f$true |
|---|
| 1500 | go4 |
|---|
| 1501 | # state = 0 |
|---|
| 1502 | .mv state$_n20c_n210$false 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1503 | .names state$_n20c_n210$false |
|---|
| 1504 | stop1 |
|---|
| 1505 | # if/else (lamp == 0) |
|---|
| 1506 | .mv state$_n20c$raw_n212 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1507 | .names state$_n20c_n20f$true state$_n20c_n210$false _n20c state$_n20c$raw_n212 |
|---|
| 1508 | - - 0 =state$_n20c_n210$false |
|---|
| 1509 | - - 1 =state$_n20c_n20f$true |
|---|
| 1510 | .mv _n217 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1511 | .names _n217 |
|---|
| 1512 | go4 |
|---|
| 1513 | .names state _n217 _n216 |
|---|
| 1514 | .def 0 |
|---|
| 1515 | - =state 1 |
|---|
| 1516 | .names _n216 _n215 |
|---|
| 1517 | 1 1 |
|---|
| 1518 | 0 0 |
|---|
| 1519 | .mv _n219 2 lit unlit |
|---|
| 1520 | .names _n219 |
|---|
| 1521 | unlit |
|---|
| 1522 | # lamp == 1 |
|---|
| 1523 | .names lamp _n219 _n218 |
|---|
| 1524 | .def 0 |
|---|
| 1525 | - =lamp 1 |
|---|
| 1526 | .names _n218 _n21a |
|---|
| 1527 | - =_n218 |
|---|
| 1528 | # state = 4 |
|---|
| 1529 | .mv state$_n218_n21b$true 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1530 | .names state$_n218_n21b$true |
|---|
| 1531 | go3 |
|---|
| 1532 | # state = 0 |
|---|
| 1533 | .mv state$_n218_n21c$false 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1534 | .names state$_n218_n21c$false |
|---|
| 1535 | stop1 |
|---|
| 1536 | # if/else (lamp == 1) |
|---|
| 1537 | .mv state$_n218$raw_n21e 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1538 | .names state$_n218_n21b$true state$_n218_n21c$false _n218 state$_n218$raw_n21e |
|---|
| 1539 | - - 0 =state$_n218_n21c$false |
|---|
| 1540 | - - 1 =state$_n218_n21b$true |
|---|
| 1541 | # case (state ) |
|---|
| 1542 | .mv state$_n215$raw_n223 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1543 | .names state$_n218$raw_n21e state _n215 state$_n215$raw_n223 |
|---|
| 1544 | - - 0 =state |
|---|
| 1545 | - - 1 =state$_n218$raw_n21e |
|---|
| 1546 | .mv state$_n209$raw_n224 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1547 | .names state$_n20c$raw_n212 state$_n215$raw_n223 _n209 state$_n209$raw_n224 |
|---|
| 1548 | - - 0 =state$_n215$raw_n223 |
|---|
| 1549 | - - 1 =state$_n20c$raw_n212 |
|---|
| 1550 | .mv state$_n1fd$raw_n228 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1551 | .names state$_n200$raw_n206 state$_n209$raw_n224 _n1fd state$_n1fd$raw_n228 |
|---|
| 1552 | - - 0 =state$_n209$raw_n224 |
|---|
| 1553 | - - 1 =state$_n200$raw_n206 |
|---|
| 1554 | .mv state$_n1f1$raw_n22c 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1555 | .names state$_n1f4$raw_n1fa state$_n1fd$raw_n228 _n1f1 state$_n1f1$raw_n22c |
|---|
| 1556 | - - 0 =state$_n1fd$raw_n228 |
|---|
| 1557 | - - 1 =state$_n1f4$raw_n1fa |
|---|
| 1558 | .mv state$_n1e5$raw_n230 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1559 | .names state$_n1e8$raw_n1ee state$_n1f1$raw_n22c _n1e5 state$_n1e5$raw_n230 |
|---|
| 1560 | - - 0 =state$_n1f1$raw_n22c |
|---|
| 1561 | - - 1 =state$_n1e8$raw_n1ee |
|---|
| 1562 | .mv state$_n1d9$raw_n234 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1563 | .names state$_n1dc$raw_n1e2 state$_n1e5$raw_n230 _n1d9 state$_n1d9$raw_n234 |
|---|
| 1564 | - - 0 =state$_n1e5$raw_n230 |
|---|
| 1565 | - - 1 =state$_n1dc$raw_n1e2 |
|---|
| 1566 | # conflict arbitrators |
|---|
| 1567 | .names out$raw_n1d0 out |
|---|
| 1568 | - =out$raw_n1d0 |
|---|
| 1569 | .names _n1d9 _n1de _n1e5 _n1ea _n1f1 _n1f6 _n1fd _n202 _n209 _n20e _n215 _n21a _n238 |
|---|
| 1570 | .def 0 |
|---|
| 1571 | 1 1 - - - - - - - - - - 1 |
|---|
| 1572 | 1 0 - - - - - - - - - - 1 |
|---|
| 1573 | 0 - 1 1 - - - - - - - - 1 |
|---|
| 1574 | 0 - 1 0 - - - - - - - - 1 |
|---|
| 1575 | 0 - 0 - 1 1 - - - - - - 1 |
|---|
| 1576 | 0 - 0 - 1 0 - - - - - - 1 |
|---|
| 1577 | 0 - 0 - 0 - 1 1 - - - - 1 |
|---|
| 1578 | 0 - 0 - 0 - 1 0 - - - - 1 |
|---|
| 1579 | 0 - 0 - 0 - 0 - 1 1 - - 1 |
|---|
| 1580 | 0 - 0 - 0 - 0 - 1 0 - - 1 |
|---|
| 1581 | 0 - 0 - 0 - 0 - 0 - 1 1 1 |
|---|
| 1582 | 0 - 0 - 0 - 0 - 0 - 1 0 1 |
|---|
| 1583 | .mv _n239 6 stop1 stop2 go1 go2 go3 go4 |
|---|
| 1584 | .names _n238 state$_n1d9$raw_n234 state _n239 |
|---|
| 1585 | 1 - - =state$_n1d9$raw_n234 |
|---|
| 1586 | 0 - - =state |
|---|
| 1587 | # non-blocking assignments |
|---|
| 1588 | # latches |
|---|
| 1589 | .r state$raw_n1cf state |
|---|
| 1590 | - =state$raw_n1cf |
|---|
| 1591 | .latch _n239 state |
|---|
| 1592 | # quasi-continuous assignment |
|---|
| 1593 | .end |
|---|
| 1594 | |
|---|
| 1595 | |
|---|
| 1596 | .model property_mod |
|---|
| 1597 | # I/O ports |
|---|
| 1598 | .inputs interpretation |
|---|
| 1599 | .inputs train |
|---|
| 1600 | |
|---|
| 1601 | .mv interpretation 2 go stop |
|---|
| 1602 | .mv state 2 good bad |
|---|
| 1603 | .mv train 3 present1 present2 absent |
|---|
| 1604 | # state = 0 |
|---|
| 1605 | .mv state$raw_n23d 2 good bad |
|---|
| 1606 | .names state$raw_n23d |
|---|
| 1607 | good |
|---|
| 1608 | # non-blocking assignments for initial |
|---|
| 1609 | .mv _n23f 3 present1 present2 absent |
|---|
| 1610 | .names _n23f |
|---|
| 1611 | present2 |
|---|
| 1612 | # train == 1 |
|---|
| 1613 | .names train _n23f _n23e |
|---|
| 1614 | .def 0 |
|---|
| 1615 | - =train 1 |
|---|
| 1616 | .mv _n241 2 go stop |
|---|
| 1617 | .names _n241 |
|---|
| 1618 | go |
|---|
| 1619 | # interpretation == 0 |
|---|
| 1620 | .names interpretation _n241 _n240 |
|---|
| 1621 | .def 0 |
|---|
| 1622 | - =interpretation 1 |
|---|
| 1623 | # (train == 1) && (interpretation == 0) |
|---|
| 1624 | .names _n23e _n240 _n242 |
|---|
| 1625 | .def 0 |
|---|
| 1626 | 1 1 1 |
|---|
| 1627 | .mv _n244 2 good bad |
|---|
| 1628 | .names _n244 |
|---|
| 1629 | bad |
|---|
| 1630 | # state == 1 |
|---|
| 1631 | .names state _n244 _n243 |
|---|
| 1632 | .def 0 |
|---|
| 1633 | - =state 1 |
|---|
| 1634 | # ((train == 1) && (interpretation == 0)) | (state == 1) |
|---|
| 1635 | .names _n242 _n243 _n245 |
|---|
| 1636 | .def 1 |
|---|
| 1637 | 0 0 0 |
|---|
| 1638 | .names _n245 _n246 |
|---|
| 1639 | - =_n245 |
|---|
| 1640 | # state = 1 |
|---|
| 1641 | .mv state$_n245_n247$true 2 good bad |
|---|
| 1642 | .names state$_n245_n247$true |
|---|
| 1643 | bad |
|---|
| 1644 | # state = 0 |
|---|
| 1645 | .mv state$_n245_n248$false 2 good bad |
|---|
| 1646 | .names state$_n245_n248$false |
|---|
| 1647 | good |
|---|
| 1648 | # if/else (((train == 1) && (interpretation == 0)) | (state == 1)) |
|---|
| 1649 | .mv state$_n245$raw_n24a 2 good bad |
|---|
| 1650 | .names state$_n245_n247$true state$_n245_n248$false _n245 state$_n245$raw_n24a |
|---|
| 1651 | - - 0 =state$_n245_n248$false |
|---|
| 1652 | - - 1 =state$_n245_n247$true |
|---|
| 1653 | # conflict arbitrators |
|---|
| 1654 | .names _n246 _n24d |
|---|
| 1655 | .def 0 |
|---|
| 1656 | 1 1 |
|---|
| 1657 | 0 1 |
|---|
| 1658 | .mv _n24e 2 good bad |
|---|
| 1659 | .names _n24d state$_n245$raw_n24a state _n24e |
|---|
| 1660 | 1 - - =state$_n245$raw_n24a |
|---|
| 1661 | 0 - - =state |
|---|
| 1662 | # non-blocking assignments |
|---|
| 1663 | # latches |
|---|
| 1664 | .r state$raw_n23d state |
|---|
| 1665 | - =state$raw_n23d |
|---|
| 1666 | .latch _n24e state |
|---|
| 1667 | # quasi-continuous assignment |
|---|
| 1668 | .end |
|---|
| 1669 | |
|---|
| 1670 | |
|---|
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