[11] | 1 | /************************************************************************/ |
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| 2 | |
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| 3 | module game(clk, consistent); |
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| 4 | input clk; |
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| 5 | output consistent; |
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| 6 | wire consistent; |
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| 7 | |
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| 8 | wire a11, a12, a13, a14, a15, a16, a17, a18, |
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| 9 | a21, a22, a23, a24, a25, a26, a27, a28, |
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| 10 | a31, a32, a33, a34, a35, a36, a37, a38, |
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| 11 | a41, a42, a43, a44, a45, a46, a47, a48, |
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| 12 | a51, a52, a53, a54, a55, a56, a57, a58, |
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| 13 | a61, a62, a63, a64, a65, a66, a67, a68, |
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| 14 | a71, a72, a73, a74, a75, a76, a77, a78, |
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| 15 | a81, a82, a83, a84, a85, a86, a87, a88; |
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| 16 | |
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| 17 | wire h1, h2, h3, h4, h5, h6, h7, h8; |
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| 18 | wire v1, v2, v3, v4, v5, v6, v7, v8; |
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| 19 | wire l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15; |
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| 20 | wire r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15; |
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| 21 | |
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| 22 | wire tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; |
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| 23 | |
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| 24 | assign a11 = $ND(0, 1); |
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| 25 | assign a12 = $ND(0, 1); |
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| 26 | assign a13 = $ND(0, 1); |
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| 27 | assign a14 = $ND(0, 1); |
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| 28 | assign a15 = $ND(0, 1); |
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| 29 | assign a16 = $ND(0, 1); |
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| 30 | assign a17 = $ND(0, 1); |
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| 31 | assign a18 = $ND(0, 1); |
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| 32 | |
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| 33 | assign a21 = $ND(0, 1); |
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| 34 | assign a22 = $ND(0, 1); |
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| 35 | assign a23 = $ND(0, 1); |
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| 36 | assign a24 = $ND(0, 1); |
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| 37 | assign a25 = $ND(0, 1); |
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| 38 | assign a26 = $ND(0, 1); |
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| 39 | assign a27 = $ND(0, 1); |
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| 40 | assign a28 = $ND(0, 1); |
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| 41 | |
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| 42 | assign a31 = $ND(0, 1); |
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| 43 | assign a32 = $ND(0, 1); |
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| 44 | assign a33 = $ND(0, 1); |
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| 45 | assign a34 = $ND(0, 1); |
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| 46 | assign a35 = $ND(0, 1); |
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| 47 | assign a36 = $ND(0, 1); |
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| 48 | assign a37 = $ND(0, 1); |
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| 49 | assign a38 = $ND(0, 1); |
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| 50 | |
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| 51 | assign a41 = $ND(0, 1); |
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| 52 | assign a42 = $ND(0, 1); |
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| 53 | assign a43 = $ND(0, 1); |
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| 54 | assign a44 = $ND(0, 1); |
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| 55 | assign a45 = $ND(0, 1); |
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| 56 | assign a46 = $ND(0, 1); |
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| 57 | assign a47 = $ND(0, 1); |
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| 58 | assign a48 = $ND(0, 1); |
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| 59 | |
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| 60 | assign a51 = $ND(0, 1); |
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| 61 | assign a52 = $ND(0, 1); |
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| 62 | assign a53 = $ND(0, 1); |
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| 63 | assign a54 = $ND(0, 1); |
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| 64 | assign a55 = $ND(0, 1); |
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| 65 | assign a56 = $ND(0, 1); |
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| 66 | assign a57 = $ND(0, 1); |
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| 67 | assign a58 = $ND(0, 1); |
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| 68 | |
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| 69 | assign a61 = $ND(0, 1); |
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| 70 | assign a62 = $ND(0, 1); |
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| 71 | assign a63 = $ND(0, 1); |
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| 72 | assign a64 = $ND(0, 1); |
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| 73 | assign a65 = $ND(0, 1); |
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| 74 | assign a66 = $ND(0, 1); |
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| 75 | assign a67 = $ND(0, 1); |
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| 76 | assign a68 = $ND(0, 1); |
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| 77 | |
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| 78 | assign a71 = $ND(0, 1); |
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| 79 | assign a72 = $ND(0, 1); |
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| 80 | assign a73 = $ND(0, 1); |
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| 81 | assign a74 = $ND(0, 1); |
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| 82 | assign a75 = $ND(0, 1); |
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| 83 | assign a76 = $ND(0, 1); |
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| 84 | assign a77 = $ND(0, 1); |
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| 85 | assign a78 = $ND(0, 1); |
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| 86 | |
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| 87 | assign a81 = $ND(0, 1); |
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| 88 | assign a82 = $ND(0, 1); |
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| 89 | assign a83 = $ND(0, 1); |
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| 90 | assign a84 = $ND(0, 1); |
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| 91 | assign a85 = $ND(0, 1); |
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| 92 | assign a86 = $ND(0, 1); |
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| 93 | assign a87 = $ND(0, 1); |
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| 94 | assign a88 = $ND(0, 1); |
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| 95 | |
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| 96 | |
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| 97 | single8 H1( clk, a11, a12, a13, a14, a15, a16, a17, a18, h1 ); |
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| 98 | single8 H2( clk, a21, a22, a23, a24, a25, a26, a27, a28, h2 ); |
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| 99 | single8 H3( clk, a31, a32, a33, a34, a35, a36, a37, a38, h3 ); |
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| 100 | single8 H4( clk, a41, a42, a43, a44, a45, a46, a47, a48, h4 ); |
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| 101 | single8 H5( clk, a51, a52, a53, a54, a55, a56, a57, a58, h5 ); |
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| 102 | none8 H6( clk, a61, a62, a63, a64, a65, a66, a67, a68, h6 ); |
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| 103 | none8 H7( clk, a71, a72, a73, a74, a75, a76, a77, a78, h7 ); |
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| 104 | none8 H8( clk, a81, a82, a83, a84, a85, a86, a87, a88, h8 ); |
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| 105 | |
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| 106 | single8 V1( clk, a11, a21, a31, a41, a51, a61, a71, a81, v1 ); |
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| 107 | single8 V2( clk, a12, a22, a32, a42, a52, a62, a72, a82, v2 ); |
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| 108 | single8 V3( clk, a13, a23, a33, a43, a53, a63, a73, a83, v3 ); |
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| 109 | single8 V4( clk, a14, a24, a34, a44, a54, a64, a74, a84, v4 ); |
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| 110 | single8 V5( clk, a15, a25, a35, a45, a55, a65, a75, a85, v5 ); |
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| 111 | none8 V6( clk, a16, a26, a36, a46, a56, a66, a76, a86, v6 ); |
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| 112 | none8 V7( clk, a17, a27, a37, a47, a57, a67, a77, a87, v7 ); |
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| 113 | none8 V8( clk, a18, a28, a38, a48, a58, a68, a78, a88, v8 ); |
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| 114 | |
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| 115 | maxone8 L1( clk, a11, 0, 0, 0, 0, 0, 0, 0, l1 ); |
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| 116 | maxone8 L2( clk, a21, a12, 0, 0, 0, 0, 0, 0, l2 ); |
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| 117 | maxone8 L3( clk, a31, a22, a13, 0, 0, 0, 0, 0, l3 ); |
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| 118 | maxone8 L4( clk, a41, a32, a23, a41, 0, 0, 0, 0, l4 ); |
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| 119 | maxone8 L5( clk, a51, a42, a33, a24, a15, 0, 0, 0, l5 ); |
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| 120 | maxone8 L6( clk, a61, a52, a43, a34, a25, a16, 0, 0, l6 ); |
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| 121 | maxone8 L7( clk, a71, a62, a53, a44, a35, a26, a17, 0, l7 ); |
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| 122 | maxone8 L8( clk, a81, a72, a63, a54, a45, a36, a27, a18, l8 ); |
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| 123 | |
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| 124 | maxone8 L9 ( clk, a82, a73, a64, a55, a46, a37, a28, 0 , l9 ); |
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| 125 | maxone8 L10( clk, a83, a74, a65, a56, a47, a38, 0 , 0 , l10 ); |
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| 126 | maxone8 L11( clk, a84, a75, a66, a57, a48, 0 , 0 , 0 , l11 ); |
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| 127 | maxone8 L12( clk, a85, a76, a67, a58, 0 , 0 , 0 , 0 , l12 ); |
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| 128 | maxone8 L13( clk, a86, a77, a68, 0 , 0 , 0 , 0 , 0 , l13 ); |
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| 129 | maxone8 L14( clk, a87, a78, 0 , 0 , 0 , 0 , 0 , 0 , l14 ); |
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| 130 | maxone8 L15( clk, a88, 0 , 0 , 0 , 0 , 0 , 0 , 0 , l15 ); |
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| 131 | |
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| 132 | maxone8 R1( clk, a18, 0, 0, 0, 0, 0, 0, 0, r1 ); |
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| 133 | maxone8 R2( clk, a28, a17, 0, 0, 0, 0, 0, 0, r2 ); |
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| 134 | maxone8 R3( clk, a38, a27, a16, 0, 0, 0, 0, 0, r3 ); |
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| 135 | maxone8 R4( clk, a48, a37, a26, a15, 0, 0, 0, 0, r4 ); |
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| 136 | maxone8 R5( clk, a58, a47, a36, a25, a14, 0, 0, 0, r5 ); |
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| 137 | maxone8 R6( clk, a68, a57, a46, a35, a24, a13, 0, 0, r6 ); |
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| 138 | maxone8 R7( clk, a78, a67, a56, a45, a34, a23, a12, 0, r7 ); |
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| 139 | maxone8 R8( clk, a88, a77, a66, a55, a44, a33, a23, a11, r8 ); |
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| 140 | |
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| 141 | maxone8 R9 ( clk, a87, a76, a65, a54, a43, a32, a21, 0 , r9 ); |
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| 142 | maxone8 R10( clk, a86, a75, a64, a53, a42, a31, 0 , 0 , r10 ); |
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| 143 | maxone8 R11( clk, a85, a74, a63, a52, a41, 0 , 0 , 0 , r11 ); |
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| 144 | maxone8 R12( clk, a84, a73, a62, a51, 0 , 0 , 0 , 0 , r12 ); |
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| 145 | maxone8 R13( clk, a83, a72, a61, 0 , 0 , 0 , 0 , 0 , r13 ); |
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| 146 | maxone8 R14( clk, a82, a71, 0 , 0 , 0 , 0 , 0 , 0 , r14 ); |
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| 147 | maxone8 R15( clk, a81, 0 , 0 , 0 , 0 , 0 , 0 , 0 , r15 ); |
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| 148 | |
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| 149 | |
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| 150 | assign tmp1 = ( h1 && h2 && h3 && h4 && h5 && h6 && h7 && h8 ); |
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| 151 | assign tmp2 = ( v1 && v2 && v3 && v4 && v5 && v6 && v7 && v8 ); |
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| 152 | assign tmp3 = ( l1 && l2 && l3 && l4 && l5 && l6 && l7 && l8 ); |
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| 153 | assign tmp4 = ( r1 && r2 && r3 && r4 && r5 && r6 && r7 && r8 ); |
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| 154 | assign tmp5 = ( l9 && l10 && l11 && l12 && l13 && l14 && l15 ); |
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| 155 | assign tmp6 = ( r9 && r10 && r11 && r12 && r13 && r14 && r15 ); |
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| 156 | |
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| 157 | assign consistent = ( tmp1 && tmp2 && tmp3 && tmp4 && tmp5 && tmp6 ); |
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| 158 | |
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| 159 | |
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| 160 | endmodule |
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| 161 | |
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| 162 | /************************************************************************/ |
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| 163 | module single8(clk, x1, x2, x3, x4, x5, x6, x7, x8, out ); |
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| 164 | input clk; |
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| 165 | input x1, x2, x3, x4, x5, x6, x7, x8; |
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| 166 | output out; |
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| 167 | |
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| 168 | wire x1, x2, x3, x4, x5, x6, x7, x8; |
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| 169 | wire out; |
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| 170 | wire tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; |
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| 171 | |
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| 172 | assign tmp1 = ( x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); |
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| 173 | assign tmp2 = ( !x1 && x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); |
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| 174 | assign tmp3 = ( !x1 && !x2 && x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); |
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| 175 | assign tmp4 = ( !x1 && !x2 && !x3 && x4 && !x5 && !x6 && !x7 && !x8 ); |
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| 176 | assign tmp5 = ( !x1 && !x2 && !x3 && !x4 && x5 && !x6 && !x7 && !x8 ); |
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| 177 | assign tmp6 = ( !x1 && !x2 && !x3 && !x4 && !x5 && x6 && !x7 && !x8 ); |
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| 178 | assign tmp7 = ( !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && x7 && !x8 ); |
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| 179 | assign tmp8 = ( !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && x8 ); |
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| 180 | |
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| 181 | |
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| 182 | assign out = ( tmp1 || tmp2 || tmp3 || tmp4 || tmp5 || tmp6 || tmp7 || tmp8 ); |
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| 183 | |
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| 184 | endmodule |
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| 185 | /************************************************************************/ |
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| 186 | module maxone8(clk, x1, x2, x3, x4, x5, x6, x7, x8, out ); |
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| 187 | input clk; |
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| 188 | input x1, x2, x3, x4, x5, x6, x7, x8; |
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| 189 | output out; |
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| 190 | |
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| 191 | wire x1, x2, x3, x4, x5, x6, x7, x8; |
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| 192 | wire out; |
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| 193 | wire tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; |
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| 194 | |
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| 195 | assign tmp0 = ( !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); |
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| 196 | assign tmp1 = ( x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); |
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| 197 | assign tmp2 = ( !x1 && x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); |
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| 198 | assign tmp3 = ( !x1 && !x2 && x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); |
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| 199 | assign tmp4 = ( !x1 && !x2 && !x3 && x4 && !x5 && !x6 && !x7 && !x8 ); |
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| 200 | assign tmp5 = ( !x1 && !x2 && !x3 && !x4 && x5 && !x6 && !x7 && !x8 ); |
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| 201 | assign tmp6 = ( !x1 && !x2 && !x3 && !x4 && !x5 && x6 && !x7 && !x8 ); |
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| 202 | assign tmp7 = ( !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && x7 && !x8 ); |
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| 203 | assign tmp8 = ( !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && x8 ); |
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| 204 | |
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| 205 | assign out = ( tmp0 || tmp1 || tmp2 || tmp3 || tmp4 || tmp5 || tmp6 || tmp7 || tmp8 ); |
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| 206 | |
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| 207 | endmodule |
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| 208 | |
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| 209 | /************************************************************************/ |
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| 210 | module none8(clk, x1, x2, x3, x4, x5, x6, x7, x8, out ); |
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| 211 | input clk; |
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| 212 | input x1, x2, x3, x4, x5, x6, x7, x8; |
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| 213 | output out; |
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| 214 | |
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| 215 | wire x1, x2, x3, x4, x5, x6, x7, x8; |
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| 216 | wire out; |
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| 217 | |
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| 218 | assign out = ( !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); |
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| 219 | |
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| 220 | endmodule |
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