source: vis_dev/vis-2.1/examples/exampleS/exampleS.mv @ 12

# vl2mv exampleS.v 
# version: 0.2
# date:    11:15:09 12/11/95 (PST)
.model resource 
# I/O ports

.mv r_st 2 I B 
.mv r_m_st 4 R G U D 
.mv m_st 4 R G U D 
.mv r_r_st 2 I B 
.subckt a0 a0 req=req  grant=grant  use=use  release=release  
# assign req  = (m_st  == R )
.mv _n2 4 R G U D 
.names _n2
R
# m_st  == 0
.names m_st _n2 _n1
.def 0
- =m_st 1
.names _n1 req$raw_n0
- =_n1
# assign use  = (m_st  == U )
.mv _n5 4 R G U D 
.names _n5
U
# m_st  == 2
.names m_st _n5 _n4
.def 0
- =m_st 1
.names _n4 use$raw_n3
- =_n4
# assign release  = (m_st  == D )
.mv _n8 4 R G U D 
.names _n8
D
# m_st  == 3
.names m_st _n8 _n7
.def 0
- =m_st 1
.names _n7 release$raw_n6
- =_n7
# m_st  = 0
.mv m_st$raw_n9 4 R G U D 
.names m_st$raw_n9
R
# non-blocking assignments for initial
# assign r_m_st  = $NDset ( 2,3 ) 
.names r_m_st
U 
D 
.mv _ne 4 R G U D 
.names _ne
R
.names m_st _ne _nd
.def 0
- =m_st 1
.names _nd  _nc
1 1
0 0
.names grant _nf
- =grant
# m_st  = 1
.mv m_st$grant_n10$true 4 R G U D 
.names m_st$grant_n10$true
G
# if/else (grant )
.mv m_st$grant$raw_n13 4 R G U D 
.names m_st$grant_n10$true m_st grant m_st$grant$raw_n13
- - 0 =m_st
- - 1 =m_st$grant_n10$true
.mv _n16 4 R G U D 
.names _n16
G
.names m_st _n16 _n15
.def 0
- =m_st 1
.names _n15  _n14
1 1
0 0
# m_st  = 2
.mv m_st$_n14_n17$true 4 R G U D 
.names m_st$_n14_n17$true
U
.mv _n1a 4 R G U D 
.names _n1a
U
.names m_st _n1a _n19
.def 0
- =m_st 1
.names _n19  _n18
1 1
0 0
# m_st  = r_m_st 
.mv m_st$_n18_n1b$true 4 R G U D 
.names r_m_st m_st$_n18_n1b$true
- =r_m_st
.mv _n1e 4 R G U D 
.names _n1e
D
.names m_st _n1e _n1d
.def 0
- =m_st 1
.names _n1d  _n1c
1 1
0 0
# m_st  = 0
.mv m_st$_n1c_n1f$true 4 R G U D 
.names m_st$_n1c_n1f$true
R
# case (m_st )
.mv m_st$_n1c$raw_n22 4 R G U D 
.names m_st$_n1c_n1f$true m_st _n1c m_st$_n1c$raw_n22
- - 0 =m_st
- - 1 =m_st$_n1c_n1f$true
.mv m_st$_n18$raw_n23 4 R G U D 
.names m_st$_n18_n1b$true m_st$_n1c$raw_n22 _n18 m_st$_n18$raw_n23
- - 0 =m_st$_n1c$raw_n22
- - 1 =m_st$_n18_n1b$true
.mv m_st$_n14$raw_n27 4 R G U D 
.names m_st$_n14_n17$true m_st$_n18$raw_n23 _n14 m_st$_n14$raw_n27
- - 0 =m_st$_n18$raw_n23
- - 1 =m_st$_n14_n17$true
.mv m_st$_nc$raw_n2b 4 R G U D 
.names m_st$grant$raw_n13 m_st$_n14$raw_n27 _nc m_st$_nc$raw_n2b
- - 0 =m_st$_n14$raw_n27
- - 1 =m_st$grant$raw_n13
# r_st  = 0
.mv r_st$raw_n2f 2 I B 
.names r_st$raw_n2f
I
# non-blocking assignments for initial
# assign grant  = (r_st  == B )
.mv _n32 2 I B 
.names _n32
B
# r_st  == 1
.names r_st _n32 _n31
.def 0
- =r_st 1
.names _n31 grant$raw_n30
- =_n31
# assign r_r_st  = $NDset ( 1,0 ) 
.names r_r_st
B 
I 
.mv _n37 2 I B 
.names _n37
I
.names r_st _n37 _n36
.def 0
- =r_st 1
.names _n36  _n35
1 1
0 0
.names req _n38
- =req
# r_st  = r_r_st 
.mv r_st$req_n39$true 2 I B 
.names r_r_st r_st$req_n39$true
- =r_r_st
# r_st  = 0
.mv r_st$req_n3a$false 2 I B 
.names r_st$req_n3a$false
I
# if/else (req )
.mv r_st$req$raw_n3c 2 I B 
.names r_st$req_n39$true r_st$req_n3a$false req r_st$req$raw_n3c
- - 0 =r_st$req_n3a$false
- - 1 =r_st$req_n39$true
.mv _n41 2 I B 
.names _n41
B
.names r_st _n41 _n40
.def 0
- =r_st 1
.names _n40  _n3f
1 1
0 0
.names release _n42
- =release
# r_st  = 0
.mv r_st$release_n43$true 2 I B 
.names r_st$release_n43$true
I
# if/else (release )
.mv r_st$release$raw_n46 2 I B 
.names r_st$release_n43$true r_st release r_st$release$raw_n46
- - 0 =r_st
- - 1 =r_st$release_n43$true
# case (r_st )
.mv r_st$_n3f$raw_n49 2 I B 
.names r_st$release$raw_n46 r_st _n3f r_st$_n3f$raw_n49
- - 0 =r_st
- - 1 =r_st$release$raw_n46
.mv r_st$_n35$raw_n4a 2 I B 
.names r_st$req$raw_n3c r_st$_n3f$raw_n49 _n35 r_st$_n35$raw_n4a
- - 0 =r_st$_n3f$raw_n49
- - 1 =r_st$req$raw_n3c
# conflict arbitrators
.names _n35 _n38 _n3f _n42 _n4e
.def 0
 1 1 - - 1
 1 0 - - 1
 0 - 1 1 1
.mv _n4f 2 I B 
.names _n4e r_st$_n35$raw_n4a r_st _n4f 
1 - - =r_st$_n35$raw_n4a
0 - - =r_st
.names release$raw_n6  release
0 0
1 1
.names req$raw_n0  req
0 0
1 1
.names use$raw_n3  use
0 0
1 1
.names _nc _nf _n14 _n18 _n1c _n5a
.def 0
 1 1 - - - 1
 0 - 1 - - 1
 0 - 0 1 - 1
 0 - 0 0 1 1
.mv _n5b 4 R G U D 
.names _n5a m_st$_nc$raw_n2b m_st _n5b 
1 - - =m_st$_nc$raw_n2b
0 - - =m_st
.names grant$raw_n30  grant
0 0
1 1
# non-blocking assignments 
# latches
.r r_st$raw_n2f r_st
- =r_st$raw_n2f
.latch _n4f r_st
.r m_st$raw_n9 m_st
- =m_st$raw_n9
.latch _n5b m_st
# quasi-continuous assignment
.end


.model a0 
# I/O ports
.inputs release
.inputs req
.inputs use
.inputs grant

# assign e0  = 1
.names e0$raw_n66
1
# assign r0  = s3  || f0 
# s3  || f0 
.names s3 f0 _n68
.def 1
0 0 0
.names _n68 r0$raw_n67
- =_n68
# assign trigger  = s0 
.names s0 trigger$raw_n69
- =s0
.subckt a0_seq0 a0_seq0 e=e0  r=r0  s=s0  f=f0  req=req  
# assign e3  = trigger 
.names trigger e3$raw_n6a
- =trigger
# assign r3  = 0
.names r3$raw_n6b
0
.subckt a0_seq3 a0_seq3 e=e3  r=r3  s=s3  f=f3  req=req  grant=grant  use=use  release=release  
# conflict arbitrators
.names r3$raw_n6b  r3
0 0
1 1
.names trigger$raw_n69  trigger
0 0
1 1
.names e0$raw_n66  e0
0 0
1 1
.names e3$raw_n6a  e3
0 0
1 1
.names r0$raw_n67  r0
0 0
1 1
# non-blocking assignments 
# latches
# quasi-continuous assignment
.end


.model a0_seq0 
# I/O ports
.inputs e
.outputs f
.inputs req
.inputs r
.outputs s

.mv st 4 S D X T 
# st  = 0
.mv st$raw_n6c 4 S D X T 
.names st$raw_n6c
S
# non-blocking assignments for initial
# assign s  = (((st  == S ) && e  && (req )))
.mv _n6f 4 S D X T 
.names _n6f
S
# st  == 0
.names st _n6f _n6e
.def 0
- =st 1
# (st  == 0) && e 
.names _n6e e _n70
.def 0
1 1 1
# (st  == 0) && e  && (req )
.names _n70 req _n71
.def 0
1 1 1
.names _n71 s$raw_n6d
- =_n71
# assign f  = (((st  == S ) && e  && !(req )) || (st  == T ))
.mv _n74 4 S D X T 
.names _n74
S
# st  == 0
.names st _n74 _n73
.def 0
- =st 1
# (st  == 0) && e 
.names _n73 e _n75
.def 0
1 1 1
.names req _n76
0 1  
1 0  
# (st  == 0) && e  && !(req )
.names _n75 _n76 _n77
.def 0
1 1 1
.mv _n79 4 S D X T 
.names _n79
T
# st  == 3
.names st _n79 _n78
.def 0
- =st 1
# ((st  == 0) && e  && !(req )) || (st  == 3)
.names _n77 _n78 _n7a
.def 1
0 0 0
.names _n7a f$raw_n72
- =_n7a
.mv _n7d 4 S D X T 
.names _n7d
S
.names st _n7d _n7c
.def 0
- =st 1
.names _n7c  _n7b
1 1
0 0
# e  && (req )
.names e req _n7e
.def 0
1 1 1
.names _n7e _n7f
- =_n7e
# st  = 0
.mv st$_n7e_n80$true 4 S D X T 
.names st$_n7e_n80$true
S
.names req _n81
0 1  
1 0  
# e  && !(req )
.names e _n81 _n82
.def 0
1 1 1
.names _n82 _n83
- =_n82
# st  = 3
.mv st$_n82_n84$true 4 S D X T 
.names st$_n82_n84$true
T
# if/else (e  && !(req ))
.mv st$_n82$raw_n87 4 S D X T 
.names st$_n82_n84$true st _n82 st$_n82$raw_n87
- - 0 =st
- - 1 =st$_n82_n84$true
# if/else (e  && (req ))
.mv st$_n7e$raw_n89 4 S D X T 
.names st$_n7e_n80$true st$_n82$raw_n87 _n7e st$_n7e$raw_n89
- - 0 =st$_n82$raw_n87
- - 1 =st$_n7e_n80$true
.names r _n8c
- =r
# st  = 0
.mv st$r_n8d$true 4 S D X T 
.names st$r_n8d$true
S
# if/else (r )
.mv st$r$raw_n90 4 S D X T 
.names st$r_n8d$true st r st$r$raw_n90
- - 0 =st
- - 1 =st$r_n8d$true
# case (st )
.mv st$_n7b$raw_n92 4 S D X T 
.names st$_n7e$raw_n89 st$r$raw_n90 _n7b st$_n7b$raw_n92
- - 0 =st$r$raw_n90
- - 1 =st$_n7e$raw_n89
# conflict arbitrators
.names f$raw_n72  f
0 0
1 1
.names s$raw_n6d  s
0 0
1 1
.names _n7b _n7f _n83 _n8c _n95
.def 0
 1 1 - - 1
 1 0 1 - 1
 0 - - 1 1
.mv _n96 4 S D X T 
.names _n95 st$_n7b$raw_n92 st _n96 
1 - - =st$_n7b$raw_n92
0 - - =st
# non-blocking assignments 
# latches
.r st$raw_n6c st
- =st$raw_n6c
.latch _n96 st
# quasi-continuous assignment
.end


.model a0_seq3 
# I/O ports
.inputs release
.inputs e
.outputs f
.inputs req
.inputs r
.outputs s
.inputs use
.inputs grant

.subckt a0_seq1 a0_seq1 e=e1  r=r1  s=s1  f=f1  req=req  grant=grant  
.subckt a0_seq2 a0_seq2 e=e2  r=r2  s=s2  f=f2  use=use  release=release  
# assign r1  = r 
.names r r1$raw_n99
- =r
# assign r2  = r 
.names r r2$raw_n9a
- =r
.subckt then then e=s1  r=r  s=e2  
# assign s  = s2 
.names s2 s$raw_n9b
- =s2
# assign f  = f1  || f2 
# f1  || f2 
.names f1 f2 _n9d
.def 1
0 0 0
.names _n9d f$raw_n9c
- =_n9d
# assign e1  = e 
.names e e1$raw_n9e
- =e
# conflict arbitrators
.names r1$raw_n99  r1
0 0
1 1
.names r2$raw_n9a  r2
0 0
1 1
.names f$raw_n9c  f
0 0
1 1
.names s$raw_n9b  s
0 0
1 1
.names e1$raw_n9e  e1
0 0
1 1
# non-blocking assignments 
# latches
# quasi-continuous assignment
.end


.model a0_seq1 
# I/O ports
.inputs e
.outputs f
.inputs req
.inputs r
.outputs s
.inputs grant

.mv st 4 S D X T 
# st  = 0
.mv st$raw_n9f 4 S D X T 
.names st$raw_n9f
S
# non-blocking assignments for initial
# assign s  = (((st  == S ) && e  && (grant )) || ((st  == X ) && (!r ) && (grant )))
.mv _na2 4 S D X T 
.names _na2
S
# st  == 0
.names st _na2 _na1
.def 0
- =st 1
# (st  == 0) && e 
.names _na1 e _na3
.def 0
1 1 1
# (st  == 0) && e  && (grant )
.names _na3 grant _na4
.def 0
1 1 1
.mv _na6 4 S D X T 
.names _na6
X
# st  == 2
.names st _na6 _na5
.def 0
- =st 1
.names r _na7
0 1  
1 0  
# (st  == 2) && (!r )
.names _na5 _na7 _na8
.def 0
1 1 1
# (st  == 2) && (!r ) && (grant )
.names _na8 grant _na9
.def 0
1 1 1
# ((st  == 0) && e  && (grant )) || ((st  == 2) && (!r ) && (grant ))
.names _na4 _na9 _naa
.def 1
0 0 0
.names _naa s$raw_na0
- =_naa
# assign f  = (((st  == S ) && e  && !(req ) && !(grant )) || ((st  == X ) && !(req ) && !(grant )) || (st  == T ))
.mv _nad 4 S D X T 
.names _nad
S
# st  == 0
.names st _nad _nac
.def 0
- =st 1
# (st  == 0) && e 
.names _nac e _nae
.def 0
1 1 1
.names req _naf
0 1  
1 0  
# (st  == 0) && e  && !(req )
.names _nae _naf _nb0
.def 0
1 1 1
.names grant _nb1
0 1  
1 0  
# (st  == 0) && e  && !(req ) && !(grant )
.names _nb0 _nb1 _nb2
.def 0
1 1 1
.mv _nb4 4 S D X T 
.names _nb4
X
# st  == 2
.names st _nb4 _nb3
.def 0
- =st 1
.names req _nb5
0 1  
1 0  
# (st  == 2) && !(req )
.names _nb3 _nb5 _nb6
.def 0
1 1 1
.names grant _nb7
0 1  
1 0  
# (st  == 2) && !(req ) && !(grant )
.names _nb6 _nb7 _nb8
.def 0
1 1 1
# ((st  == 0) && e  && !(req ) && !(grant )) || ((st  == 2) && !(req ) && !(grant ))
.names _nb2 _nb8 _nb9
.def 1
0 0 0
.mv _nbb 4 S D X T 
.names _nbb
T
# st  == 3
.names st _nbb _nba
.def 0
- =st 1
# ((st  == 0) && e  && !(req ) && !(grant )) || ((st  == 2) && !(req ) && !(grant )) || (st  == 3)
.names _nb9 _nba _nbc
.def 1
0 0 0
.names _nbc f$raw_nab
- =_nbc
.mv _nbf 4 S D X T 
.names _nbf
S
.names st _nbf _nbe
.def 0
- =st 1
.names _nbe  _nbd
1 1
0 0
# e  && (grant )
.names e grant _nc0
.def 0
1 1 1
.names _nc0 _nc1
- =_nc0
# st  = 0
.mv st$_nc0_nc2$true 4 S D X T 
.names st$_nc0_nc2$true
S
# e  && (req )
.names e req _nc3
.def 0
1 1 1
.names _nc3 _nc4
- =_nc3
# st  = 2
.mv st$_nc3_nc5$true 4 S D X T 
.names st$_nc3_nc5$true
X
.names req _nc6
0 1  
1 0  
# e  && !(req )
.names e _nc6 _nc7
.def 0
1 1 1
.names grant _nc8
0 1  
1 0  
# e  && !(req ) && !(grant )
.names _nc7 _nc8 _nc9
.def 0
1 1 1
.names _nc9 _nca
- =_nc9
# st  = 3
.mv st$_nc9_ncb$true 4 S D X T 
.names st$_nc9_ncb$true
T
# if/else (e  && !(req ) && !(grant ))
.mv st$_nc9$raw_nce 4 S D X T 
.names st$_nc9_ncb$true st _nc9 st$_nc9$raw_nce
- - 0 =st
- - 1 =st$_nc9_ncb$true
# if/else (e  && (req ))
.mv st$_nc3$raw_nd0 4 S D X T 
.names st$_nc3_nc5$true st$_nc9$raw_nce _nc3 st$_nc3$raw_nd0
- - 0 =st$_nc9$raw_nce
- - 1 =st$_nc3_nc5$true
# if/else (e  && (grant ))
.mv st$_nc0$raw_nd4 4 S D X T 
.names st$_nc0_nc2$true st$_nc3$raw_nd0 _nc0 st$_nc0$raw_nd4
- - 0 =st$_nc3$raw_nd0
- - 1 =st$_nc0_nc2$true
.mv _nd9 4 S D X T 
.names _nd9
X
.names st _nd9 _nd8
.def 0
- =st 1
.names _nd8  _nd7
1 1
0 0
# r  || (grant )
.names r grant _nda
.def 1
0 0 0
.names _nda _ndb
- =_nda
# st  = 0
.mv st$_nda_ndc$true 4 S D X T 
.names st$_nda_ndc$true
S
.names req _ndd
0 1  
1 0  
.names grant _nde
0 1  
1 0  
# !(req ) && !(grant )
.names _ndd _nde _ndf
.def 0
1 1 1
.names _ndf _ne0
- =_ndf
# st  = 3
.mv st$_ndf_ne1$true 4 S D X T 
.names st$_ndf_ne1$true
T
# if/else (!(req ) && !(grant ))
.mv st$_ndf$raw_ne4 4 S D X T 
.names st$_ndf_ne1$true st _ndf st$_ndf$raw_ne4
- - 0 =st
- - 1 =st$_ndf_ne1$true
# if/else (r  || (grant ))
.mv st$_nda$raw_ne6 4 S D X T 
.names st$_nda_ndc$true st$_ndf$raw_ne4 _nda st$_nda$raw_ne6
- - 0 =st$_ndf$raw_ne4
- - 1 =st$_nda_ndc$true
.names r _ne9
- =r
# st  = 0
.mv st$r_nea$true 4 S D X T 
.names st$r_nea$true
S
# if/else (r )
.mv st$r$raw_ned 4 S D X T 
.names st$r_nea$true st r st$r$raw_ned
- - 0 =st
- - 1 =st$r_nea$true
# case (st )
.mv st$_nd7$raw_nef 4 S D X T 
.names st$_nda$raw_ne6 st$r$raw_ned _nd7 st$_nd7$raw_nef
- - 0 =st$r$raw_ned
- - 1 =st$_nda$raw_ne6
.mv st$_nbd$raw_nf3 4 S D X T 
.names st$_nc0$raw_nd4 st$_nd7$raw_nef _nbd st$_nbd$raw_nf3
- - 0 =st$_nd7$raw_nef
- - 1 =st$_nc0$raw_nd4
# conflict arbitrators
.names f$raw_nab  f
0 0
1 1
.names s$raw_na0  s
0 0
1 1
.names _nbd _nc1 _nc4 _nca _nd7 _ndb _ne0 _ne9 _nf6
.def 0
 1 1 - - - - - - 1
 1 0 1 - - - - - 1
 1 0 0 1 - - - - 1
 0 - - - 1 1 - - 1
 0 - - - 1 0 1 - 1
 0 - - - 0 - - 1 1
.mv _nf7 4 S D X T 
.names _nf6 st$_nbd$raw_nf3 st _nf7 
1 - - =st$_nbd$raw_nf3
0 - - =st
# non-blocking assignments 
# latches
.r st$raw_n9f st
- =st$raw_n9f
.latch _nf7 st
# quasi-continuous assignment
.end


.model a0_seq2 
# I/O ports
.inputs release
.inputs e
.outputs f
.inputs r
.outputs s
.inputs use

.mv st 4 S D X T 
# st  = 0
.mv st$raw_nfa 4 S D X T 
.names st$raw_nfa
S
# non-blocking assignments for initial
# assign s  = (((st  == S ) && e  && (release )) || ((st  == X ) && (!r ) && (release )))
.mv _nfd 4 S D X T 
.names _nfd
S
# st  == 0
.names st _nfd _nfc
.def 0
- =st 1
# (st  == 0) && e 
.names _nfc e _nfe
.def 0
1 1 1
# (st  == 0) && e  && (release )
.names _nfe release _nff
.def 0
1 1 1
.mv _n101 4 S D X T 
.names _n101
X
# st  == 2
.names st _n101 _n100
.def 0
- =st 1
.names r _n102
0 1  
1 0  
# (st  == 2) && (!r )
.names _n100 _n102 _n103
.def 0
1 1 1
# (st  == 2) && (!r ) && (release )
.names _n103 release _n104
.def 0
1 1 1
# ((st  == 0) && e  && (release )) || ((st  == 2) && (!r ) && (release ))
.names _nff _n104 _n105
.def 1
0 0 0
.names _n105 s$raw_nfb
- =_n105
# assign f  = (((st  == S ) && e  && !(use ) && !(release )) || ((st  == X ) && !(use ) && !(release )) || (st  == T ))
.mv _n108 4 S D X T 
.names _n108
S
# st  == 0
.names st _n108 _n107
.def 0
- =st 1
# (st  == 0) && e 
.names _n107 e _n109
.def 0
1 1 1
.names use _n10a
0 1  
1 0  
# (st  == 0) && e  && !(use )
.names _n109 _n10a _n10b
.def 0
1 1 1
.names release _n10c
0 1  
1 0  
# (st  == 0) && e  && !(use ) && !(release )
.names _n10b _n10c _n10d
.def 0
1 1 1
.mv _n10f 4 S D X T 
.names _n10f
X
# st  == 2
.names st _n10f _n10e
.def 0
- =st 1
.names use _n110
0 1  
1 0  
# (st  == 2) && !(use )
.names _n10e _n110 _n111
.def 0
1 1 1
.names release _n112
0 1  
1 0  
# (st  == 2) && !(use ) && !(release )
.names _n111 _n112 _n113
.def 0
1 1 1
# ((st  == 0) && e  && !(use ) && !(release )) || ((st  == 2) && !(use ) && !(release ))
.names _n10d _n113 _n114
.def 1
0 0 0
.mv _n116 4 S D X T 
.names _n116
T
# st  == 3
.names st _n116 _n115
.def 0
- =st 1
# ((st  == 0) && e  && !(use ) && !(release )) || ((st  == 2) && !(use ) && !(release )) || (st  == 3)
.names _n114 _n115 _n117
.def 1
0 0 0
.names _n117 f$raw_n106
- =_n117
.mv _n11a 4 S D X T 
.names _n11a
S
.names st _n11a _n119
.def 0
- =st 1
.names _n119  _n118
1 1
0 0
# e  && (release )
.names e release _n11b
.def 0
1 1 1
.names _n11b _n11c
- =_n11b
# st  = 0
.mv st$_n11b_n11d$true 4 S D X T 
.names st$_n11b_n11d$true
S
# e  && (use )
.names e use _n11e
.def 0
1 1 1
.names _n11e _n11f
- =_n11e
# st  = 2
.mv st$_n11e_n120$true 4 S D X T 
.names st$_n11e_n120$true
X
.names use _n121
0 1  
1 0  
# e  && !(use )
.names e _n121 _n122
.def 0
1 1 1
.names release _n123
0 1  
1 0  
# e  && !(use ) && !(release )
.names _n122 _n123 _n124
.def 0
1 1 1
.names _n124 _n125
- =_n124
# st  = 3
.mv st$_n124_n126$true 4 S D X T 
.names st$_n124_n126$true
T
# if/else (e  && !(use ) && !(release ))
.mv st$_n124$raw_n129 4 S D X T 
.names st$_n124_n126$true st _n124 st$_n124$raw_n129
- - 0 =st
- - 1 =st$_n124_n126$true
# if/else (e  && (use ))
.mv st$_n11e$raw_n12b 4 S D X T 
.names st$_n11e_n120$true st$_n124$raw_n129 _n11e st$_n11e$raw_n12b
- - 0 =st$_n124$raw_n129
- - 1 =st$_n11e_n120$true
# if/else (e  && (release ))
.mv st$_n11b$raw_n12f 4 S D X T 
.names st$_n11b_n11d$true st$_n11e$raw_n12b _n11b st$_n11b$raw_n12f
- - 0 =st$_n11e$raw_n12b
- - 1 =st$_n11b_n11d$true
.mv _n134 4 S D X T 
.names _n134
X
.names st _n134 _n133
.def 0
- =st 1
.names _n133  _n132
1 1
0 0
# r  || (release )
.names r release _n135
.def 1
0 0 0
.names _n135 _n136
- =_n135
# st  = 0
.mv st$_n135_n137$true 4 S D X T 
.names st$_n135_n137$true
S
.names use _n138
0 1  
1 0  
.names release _n139
0 1  
1 0  
# !(use ) && !(release )
.names _n138 _n139 _n13a
.def 0
1 1 1
.names _n13a _n13b
- =_n13a
# st  = 3
.mv st$_n13a_n13c$true 4 S D X T 
.names st$_n13a_n13c$true
T
# if/else (!(use ) && !(release ))
.mv st$_n13a$raw_n13f 4 S D X T 
.names st$_n13a_n13c$true st _n13a st$_n13a$raw_n13f
- - 0 =st
- - 1 =st$_n13a_n13c$true
# if/else (r  || (release ))
.mv st$_n135$raw_n141 4 S D X T 
.names st$_n135_n137$true st$_n13a$raw_n13f _n135 st$_n135$raw_n141
- - 0 =st$_n13a$raw_n13f
- - 1 =st$_n135_n137$true
.names r _n144
- =r
# st  = 0
.mv st$r_n145$true 4 S D X T 
.names st$r_n145$true
S
# if/else (r )
.mv st$r$raw_n148 4 S D X T 
.names st$r_n145$true st r st$r$raw_n148
- - 0 =st
- - 1 =st$r_n145$true
# case (st )
.mv st$_n132$raw_n14a 4 S D X T 
.names st$_n135$raw_n141 st$r$raw_n148 _n132 st$_n132$raw_n14a
- - 0 =st$r$raw_n148
- - 1 =st$_n135$raw_n141
.mv st$_n118$raw_n14e 4 S D X T 
.names st$_n11b$raw_n12f st$_n132$raw_n14a _n118 st$_n118$raw_n14e
- - 0 =st$_n132$raw_n14a
- - 1 =st$_n11b$raw_n12f
# conflict arbitrators
.names f$raw_n106  f
0 0
1 1
.names s$raw_nfb  s
0 0
1 1
.names _n118 _n11c _n11f _n125 _n132 _n136 _n13b _n144 _n151
.def 0
 1 1 - - - - - - 1
 1 0 1 - - - - - 1
 1 0 0 1 - - - - 1
 0 - - - 1 1 - - 1
 0 - - - 1 0 1 - 1
 0 - - - 0 - - 1 1
.mv _n152 4 S D X T 
.names _n151 st$_n118$raw_n14e st _n152 
1 - - =st$_n118$raw_n14e
0 - - =st
# non-blocking assignments 
# latches
.r st$raw_nfa st
- =st$raw_nfa
.latch _n152 st
# quasi-continuous assignment
.end


.model then 
# I/O ports
.inputs e
.inputs r
.outputs s

.mv st 4 S D X T 
# st  = 0
.mv st$raw_n155 4 S D X T 
.names st$raw_n155
S
# non-blocking assignments for initial
# assign s  = (st  == D )
.mv _n158 4 S D X T 
.names _n158
D
# st  == 1
.names st _n158 _n157
.def 0
- =st 1
.names _n157 s$raw_n156
- =_n157
.mv _n15b 4 S D X T 
.names _n15b
S
.names st _n15b _n15a
.def 0
- =st 1
.names _n15a  _n159
1 1
0 0
.names e _n15c
- =e
# st  = 2
.mv st$e_n15d$true 4 S D X T 
.names st$e_n15d$true
X
# if/else (e )
.mv st$e$raw_n160 4 S D X T 
.names st$e_n15d$true st e st$e$raw_n160
- - 0 =st
- - 1 =st$e_n15d$true
.mv _n163 4 S D X T 
.names _n163
X
.names st _n163 _n162
.def 0
- =st 1
.names _n162  _n161
1 1
0 0
# st  = 1
.mv st$_n161_n164$true 4 S D X T 
.names st$_n161_n164$true
D
.names r _n165
- =r
# st  = 0
.mv st$r_n166$true 4 S D X T 
.names st$r_n166$true
S
# if/else (r )
.mv st$r$raw_n169 4 S D X T 
.names st$r_n166$true st r st$r$raw_n169
- - 0 =st
- - 1 =st$r_n166$true
# case (st )
.mv st$_n161$raw_n16b 4 S D X T 
.names st$_n161_n164$true st$r$raw_n169 _n161 st$_n161$raw_n16b
- - 0 =st$r$raw_n169
- - 1 =st$_n161_n164$true
.mv st$_n159$raw_n16f 4 S D X T 
.names st$e$raw_n160 st$_n161$raw_n16b _n159 st$_n159$raw_n16f
- - 0 =st$_n161$raw_n16b
- - 1 =st$e$raw_n160
# conflict arbitrators
.names s$raw_n156  s
0 0
1 1
.names _n159 _n15c _n161 _n165 _n172
.def 0
 1 1 - - 1
 0 - 1 - 1
 0 - 0 1 1
.mv _n173 4 S D X T 
.names _n172 st$_n159$raw_n16f st _n173 
1 - - =st$_n159$raw_n16f
0 - - =st
# non-blocking assignments 
# latches
.r st$raw_n155 st
- =st$raw_n155
.latch _n173 st
# quasi-continuous assignment
.end