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s1269.ord @ 12

Last change on this file since 12 was 11, checked in by cecile, 13 years ago
Add vis
File size: 4.6 KB

Line
1	# vis release 1.4 (compiled 20-Jun-02 at 7:12 PM)
2	# network name: unnamed
3	# generated: Tue Jul 2 10:55:31 2002
4	#
5	# name type mddId vals levs
6	TESTMODE primary-input 17 2 (0)
7	oLDALUout$NS shadow 1 2 (1)
8	oLDALUout latch 0 2 (2)
9	qLDALUout latch 90 2 (3)
10	qLDALUout$NS shadow 91 2 (4)
11	qShiftRight latch 64 2 (5)
12	qShiftRight$NS shadow 65 2 (6)
13	I681 latch 9 2 (7)
14	I681$NS shadow 10 2 (8)
15	I680 latch 3 2 (9)
16	I680$NS shadow 4 2 (10)
17	I679$NS shadow 8 2 (11)
18	I679 latch 7 2 (12)
19	qPass1$NS shadow 27 2 (13)
20	qPass1 latch 26 2 (14)
21	I683$NS shadow 15 2 (15)
22	I683 latch 14 2 (16)
23	INS_2 primary-input 21 2 (17)
24	qINSo_2$NS shadow 61 2 (18)
25	qINSo_2 latch 60 2 (19)
26	INS_1 primary-input 16 2 (20)
27	qINSo_1$NS shadow 19 2 (21)
28	qINSo_1 latch 18 2 (22)
29	qINSo_0 latch 62 2 (23)
30	qINSo_0$NS shadow 63 2 (24)
31	INS_0 primary-input 20 2 (25)
32	qPass2 latch 22 2 (26)
33	qPass2$NS shadow 23 2 (27)
34	I682 latch 5 2 (28)
35	I682$NS shadow 6 2 (29)
36	MQ_q_0 latch 11 2 (30)
37	MQ_q_0$NS shadow 12 2 (31)
38	LDAcc primary-input 81 2 (32)
39	DR_q_7 latch 56 2 (33)
40	DR_q_7$NS shadow 57 2 (34)
41	STDR primary-input 48 2 (35)
42	Acc_q_7 latch 58 2 (36)
43	Acc_q_7$NS shadow 59 2 (37)
44	LDMQ primary-input 78 2 (38)
45	inBUS_7 primary-input 88 2 (39)
46	inBUS_0 primary-input 82 2 (40)
47	DR_q_0 latch 46 2 (41)
48	DR_q_0$NS shadow 47 2 (42)
49	Acc_q_0 latch 49 2 (43)
50	Acc_q_0$NS shadow 50 2 (44)
51	MQ_q_7$NS shadow 80 2 (45)
52	MQ_q_7 latch 79 2 (46)
53	Acc_q_1 latch 44 2 (47)
54	Acc_q_1$NS shadow 45 2 (48)
55	DR_q_1 latch 42 2 (49)
56	DR_q_1$NS shadow 43 2 (50)
57	inBUS_1 primary-input 83 2 (51)
58	MQ_q_1 latch 76 2 (52)
59	MQ_q_1$NS shadow 77 2 (53)
60	Acc_q_2 latch 32 2 (54)
61	Acc_q_2$NS shadow 33 2 (55)
62	DR_q_2 latch 30 2 (56)
63	DR_q_2$NS shadow 31 2 (57)
64	inBUS_2 primary-input 84 2 (58)
65	MQ_q_2 latch 74 2 (59)
66	MQ_q_2$NS shadow 75 2 (60)
67	DR_q_3 latch 24 2 (61)
68	DR_q_3$NS shadow 25 2 (62)
69	Acc_q_3 latch 28 2 (63)
70	Acc_q_3$NS shadow 29 2 (64)
71	inBUS_3 primary-input 85 2 (65)
72	MQ_q_3 latch 72 2 (66)
73	MQ_q_3$NS shadow 73 2 (67)
74	LDDR primary-input 2 2 (68)
75	Acc_q_4$NS shadow 37 2 (69)
76	Acc_q_4 latch 36 2 (70)
77	DR_q_4 latch 34 2 (71)
78	DR_q_4$NS shadow 35 2 (72)
79	inBUS_4 primary-input 87 2 (73)
80	MQ_q_4 latch 70 2 (74)
81	MQ_q_4$NS shadow 71 2 (75)
82	DR_q_5 latch 38 2 (76)
83	DR_q_5$NS shadow 39 2 (77)
84	DR_q_6$NS shadow 53 2 (78)
85	DR_q_6 latch 52 2 (79)
86	inBUS_6 primary-input 89 2 (80)
87	inBUS_5 primary-input 86 2 (81)
88	Acc_q_5 latch 40 2 (82)
89	Acc_q_5$NS shadow 41 2 (83)
90	MQ_q_5 latch 68 2 (84)
91	MQ_q_5$NS shadow 69 2 (85)
92	STMQ primary-input 13 2 (86)
93	MQ_q_6 latch 66 2 (87)
94	MQ_q_6$NS shadow 67 2 (88)
95	STAcc primary-input 51 2 (89)
96	Acc_q_6 latch 54 2 (90)
97	Acc_q_6$NS shadow 55 2 (91)

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