[11] | 1 | /************************************************************************** |
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| 2 | |
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| 3 | This is a simple tree arbiter, adapted from Dills' thesis p 89. |
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| 4 | There are four processors which |
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| 5 | share a single resource. A token defines which processor has the |
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| 6 | resource. The arbiter cells have two children and one parent. |
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| 7 | An arbiter can request the token, release it, etc. |
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| 8 | |
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| 9 | Adnan Aziz |
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| 10 | July 10, 1996 |
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| 11 | UT Austin |
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| 12 | |
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| 13 | ***************************************************************************/ |
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| 14 | |
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| 15 | /* |
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| 16 | * Symbolic variables. |
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| 17 | * |
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| 18 | */ |
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| 19 | typedef enum {myTRUE, myFALSE} boolean; |
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| 20 | typedef enum {idle, request, lock, release} handShakeType; |
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| 21 | |
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| 22 | /* |
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| 23 | * The inteconnections between the processors and the cells. |
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| 24 | * |
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| 25 | */ |
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| 26 | module main( clk ); |
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| 27 | input clk; |
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| 28 | |
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| 29 | boolean wire xa, ya, sa; |
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| 30 | handShakeType wire xr, yr, sr; |
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| 31 | |
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| 32 | boolean wire constTRUE; |
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| 33 | |
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| 34 | |
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| 35 | assign sa = myFALSE; |
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| 36 | assign constTRUE = myTRUE; |
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| 37 | |
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| 38 | arbitCell F0( clk, constTRUE, xr, yr, xa, ya, sr, sa ); |
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| 39 | fourCells G1( clk, xa, xr ); |
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| 40 | fourCells G2( clk, ya, yr ); |
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| 41 | |
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| 42 | endmodule |
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| 43 | |
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| 44 | |
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| 45 | module fourCells( clk, sa, sr ); |
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| 46 | input clk; |
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| 47 | input sa; |
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| 48 | output sr; |
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| 49 | |
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| 50 | boolean wire ua1, ua2, ua3, ua4, xa, ya, sa; |
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| 51 | handShakeType wire ur1, ur2, ur3, ur4, xr, yr, sr; |
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| 52 | |
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| 53 | wire[0:1] procChoice; |
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| 54 | |
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| 55 | boolean wire constTRUE, constFALSE; |
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| 56 | |
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| 57 | assign constTRUE = myTRUE; |
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| 58 | assign constFALSE = myFALSE; |
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| 59 | |
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| 60 | arbitCell C0 ( clk, constFALSE, xr, yr, xa, ya, sr, sa ); |
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| 61 | arbitCell C1 ( clk, constFALSE, ur1, ur2, ua1, ua2, xr, xa ); |
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| 62 | arbitCell C2 ( clk, constFALSE, ur3, ur4, ua3, ua4, yr, ya ); |
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| 63 | |
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| 64 | procModel P1( clk, ua1, ur1 ); |
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| 65 | procModel P2( clk, ua2, ur2 ); |
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| 66 | procModel P3( clk, ua3, ur3 ); |
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| 67 | procModel P4( clk, ua4, ur4 ); |
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| 68 | |
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| 69 | endmodule |
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| 70 | |
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| 71 | |
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| 72 | /* |
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| 73 | * The arbiter cell has two inputs from children and two outputs to chidren. |
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| 74 | * One input from parent, and one output to parent. The latch holdToken corresponds |
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| 75 | * to whether the cell holds the token. The latches prevLeft and prevRight are |
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| 76 | * used to keep track of which way the token went last, to impart fairness |
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| 77 | * in the scheduling of the children. |
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| 78 | * |
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| 79 | */ |
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| 80 | |
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| 81 | |
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| 82 | /* |
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| 83 | * Add comments |
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| 84 | */ |
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| 85 | module procModel(clk, ack, req ); |
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| 86 | input clk; |
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| 87 | input ack; |
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| 88 | output req; |
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| 89 | |
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| 90 | boolean wire ack; |
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| 91 | handShakeType wire req; |
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| 92 | wire randChoice; |
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| 93 | |
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| 94 | assign req = procState; |
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| 95 | assign randChoice = $ND(0,1); |
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| 96 | |
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| 97 | handShakeType reg procState; |
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| 98 | |
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| 99 | initial procState = idle; |
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| 100 | |
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| 101 | always @(posedge clk) begin |
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| 102 | |
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| 103 | if ( procState == idle && (randChoice == 1) ) |
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| 104 | begin |
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| 105 | procState = request; |
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| 106 | end |
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| 107 | else if ( procState == request && ack == myTRUE ) |
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| 108 | begin |
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| 109 | procState = lock; |
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| 110 | end |
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| 111 | else if ( procState == lock && (randChoice == 1 ) ) |
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| 112 | begin |
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| 113 | procState = release; |
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| 114 | end |
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| 115 | else if ( procState == release ) |
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| 116 | begin |
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| 117 | procState = idle; |
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| 118 | end |
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| 119 | end |
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| 120 | |
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| 121 | endmodule |
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| 122 | |
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| 123 | |
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| 124 | |
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| 125 | module arbitCell(clk, topCell, urLeft, urRight, uaLeft, uaRight, xr, xa); |
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| 126 | input clk; |
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| 127 | input topCell, urLeft, urRight, xa; |
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| 128 | output uaLeft, uaRight, xr; |
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| 129 | |
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| 130 | boolean wire topCell, uaLeft, uaRight, xa; |
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| 131 | handShakeType wire urLeft, urRight, xr; |
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| 132 | |
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| 133 | boolean wire uaLeft, uaRight; |
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| 134 | |
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| 135 | boolean reg prevLeft, prevRight; |
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| 136 | initial prevLeft = myFALSE; |
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| 137 | initial prevRight = myTRUE; |
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| 138 | |
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| 139 | boolean reg processedLeft, processedRight; |
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| 140 | initial processedLeft = myFALSE; |
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| 141 | initial processedRight = myFALSE; |
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| 142 | |
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| 143 | boolean wire mustGiveParent; /* essentially a macro for checking if must release the token to parent */ |
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| 144 | assign mustGiveParent = ( processedLeft == myTRUE ) && ( processedRight == myTRUE ) |
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| 145 | && ( !( topCell == myTRUE ) ) ? myTRUE : myFALSE; |
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| 146 | |
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| 147 | boolean reg holdToken; |
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| 148 | initial holdToken = topCell; |
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| 149 | |
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| 150 | boolean wire childOwns; /* essentially a macro for checking if a descendant owns the token */ |
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| 151 | assign childOwns = ( urLeft == lock || urRight == lock ) ? myTRUE : myFALSE; |
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| 152 | |
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| 153 | boolean wire giveChild; /* essentially a macro for checking if a child is being given the token */ |
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| 154 | assign giveChild = ( uaLeft == myTRUE || uaRight == myTRUE ) ? myTRUE : myFALSE; |
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| 155 | |
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| 156 | /* |
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| 157 | * Condition under which the token is given to the left child |
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| 158 | * Must own token, have request from left, and either no request from right or if there is |
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| 159 | * a request from the right it, should be lefts turn (since right went the last time |
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| 160 | * |
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| 161 | */ |
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| 162 | assign uaLeft = ( !( mustGiveParent == myTRUE ) && ( holdToken == myTRUE && urLeft == request |
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| 163 | && ( ! ( urRight == request ) || prevRight == myTRUE ) ) ) ? myTRUE : myFALSE; |
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| 164 | |
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| 165 | /* |
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| 166 | * same as above for right |
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| 167 | * |
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| 168 | */ |
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| 169 | assign uaRight = ( !( mustGiveParent == myTRUE ) && ( holdToken == myTRUE && urRight == request |
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| 170 | && ( ! ( urLeft == request ) || prevLeft == myTRUE ) ) ) ? myTRUE : myFALSE; |
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| 171 | |
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| 172 | /* |
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| 173 | * signal to parent: |
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| 174 | * |
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| 175 | * 1. request if dont own the token, |
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| 176 | * 2. lock if descendant has locked the token |
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| 177 | * 3. release if child has released token |
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| 178 | * 4. idle otherwise |
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| 179 | * |
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| 180 | */ |
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| 181 | assign xr = ( holdToken == myFALSE && ( urLeft == request || urRight == request ) ) |
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| 182 | ? request : |
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| 183 | ( childOwns == myTRUE ) |
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| 184 | ? lock : |
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| 185 | ( holdToken == myTRUE && ( ( ( mustGiveParent == myTRUE ) || |
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| 186 | ! ( ( urLeft == request || urRight == request ) ) ) |
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| 187 | && !( topCell == myTRUE ) ) ) |
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| 188 | ? release : idle; |
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| 189 | |
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| 190 | always @(posedge clk) begin |
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| 191 | |
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| 192 | /* |
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| 193 | * keep track of whether we hold the token or not |
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| 194 | * |
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| 195 | */ |
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| 196 | |
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| 197 | if ( xa == myTRUE ) |
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| 198 | begin |
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| 199 | holdToken = myTRUE; |
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| 200 | end |
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| 201 | else if ( giveChild == myTRUE ) |
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| 202 | begin |
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| 203 | holdToken = myFALSE; |
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| 204 | end |
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| 205 | else if ( urLeft == release || urRight == release ) |
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| 206 | begin |
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| 207 | holdToken = myTRUE; |
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| 208 | end |
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| 209 | else if ( xr == release ) |
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| 210 | begin |
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| 211 | holdToken = myFALSE; |
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| 212 | end |
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| 213 | |
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| 214 | /* |
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| 215 | * keep track of which child got the token last |
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| 216 | * |
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| 217 | */ |
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| 218 | if ( uaLeft == myTRUE ) |
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| 219 | begin |
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| 220 | prevLeft = myTRUE; |
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| 221 | prevRight = myFALSE; |
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| 222 | end |
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| 223 | else if ( uaRight == myTRUE ) |
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| 224 | begin |
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| 225 | prevLeft = myFALSE; |
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| 226 | prevRight = myTRUE; |
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| 227 | end |
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| 228 | |
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| 229 | /* |
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| 230 | * child has finished processing the token |
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| 231 | * |
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| 232 | */ |
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| 233 | |
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| 234 | if ( urLeft == release ) |
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| 235 | begin |
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| 236 | processedLeft = myTRUE; |
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| 237 | end |
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| 238 | else if ( urRight == release ) |
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| 239 | begin |
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| 240 | processedRight = myTRUE; |
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| 241 | end |
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| 242 | /* |
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| 243 | * if we have given the token to both children, must now give it up |
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| 244 | * |
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| 245 | */ |
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| 246 | else if ( ( processedLeft == myTRUE ) && ( processedRight == myTRUE ) ) |
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| 247 | begin |
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| 248 | processedLeft = myFALSE; |
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| 249 | processedRight = myFALSE; |
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| 250 | end |
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| 251 | |
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| 252 | end |
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| 253 | |
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| 254 | endmodule |
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