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| 2 | spfd_pdlo - Perform SPFD-based simultaneous placement and logic optimization. |
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| 3 | _________________________________________________________________ |
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| 4 | |
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| 5 | spfd_pdlo [-D <depth>] [-h] [-n <file>] [-r] [-t <sec>] [-v <n>] [-w |
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| 6 | <file>] net_file arch_file place_file route_file |
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| 7 | |
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| 8 | This command performs SPFD-based combined logic and placement |
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| 9 | optimization of combinational circuits mapped to LUT-based FPGAs to |
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| 10 | improve circuit area and speed. The flexibilities in the circuit are |
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| 11 | represented by SPFDs. The following references explain in detail the |
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| 12 | theory behind SPFDs. |
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| 13 | |
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| 14 | S. Yamashita, H. Sawada, and A. Nagoya. A new method to express |
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| 15 | functional permissibilities for LUT based FPGAs and its applications. |
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| 16 | In International Conference on Computer Aided Design, pages 254-261, |
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| 17 | 1996. |
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| 18 | |
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| 19 | Subarnarekha Sinha and Robert K. Brayton. Implementation and use of |
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| 20 | SPFDs in optimizaing Boolean networks. In International Conference on |
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| 21 | Computer Aided Design, 1998. |
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| 22 | |
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| 23 | The command implements a technique that tightly links the logic and |
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| 24 | placement optimization steps. The algorithm is based on simulated |
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| 25 | annealing. Two types of moves, directed towards global reduction in |
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| 26 | the cost function (total wire length), are accepted by the simulated |
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| 27 | annealing algorithm: (1) wire removal/replacement, and (2) swapping of |
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| 28 | a pair of blocks in the FPGA. Feedback from placement is valuable in |
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| 29 | making an informed choice of a target wire during logic optimization |
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| 30 | moves. The logic optimization steps performed are similar to those of |
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| 31 | spfd_pilo, except that the placement information is now used instead |
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| 32 | of the fanout count. More information on this technique can be found |
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| 33 | in : |
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| 34 | |
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| 35 | Balakrishna Kumthekar and Fabio Somenzi. Power and delay reduction via |
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| 36 | simultaneous logic and placement optimization in FPGAs. In Design, |
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| 37 | Automation and Test in Europe, 2000. |
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| 38 | |
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| 39 | The command produces a placement file which is used by VPR for |
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| 40 | routing. |
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| 41 | |
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| 42 | This command can be used only if VIS is linked with VPR 4.22 |
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| 43 | (Versatile Place and Route), the FPGA place and route tool [1]VPR, |
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| 44 | from the University of Toronto. Please follow the instructions |
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| 45 | provided in the release notes to use VPR with VIS. You can also |
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| 46 | contact kumtheka@avanticorp.com if you need more help. |
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| 47 | |
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| 48 | Before calling this command a network should be created for the design |
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| 49 | (use flatten_hierarchy) and MDD ids for every node in the network |
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| 50 | should be created (static_order -o all -n append). Dynamic variable |
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| 51 | ordering (dvo -e sift) can be enabled to reduce BDD sizes. |
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| 52 | |
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| 53 | Command options: |
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| 54 | |
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| 55 | -D <depth> |
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| 56 | A cluster is computed which includes nodes within the specified |
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| 57 | 'depth'. The default value is 1. |
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| 58 | |
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| 59 | -n <file> |
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| 60 | File to output the optimized circuit in VPR's .net format. |
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| 61 | |
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| 62 | -r |
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| 63 | Do not reprogram LUTs if no structural changes have been |
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| 64 | performed with in the cluster, i.e., if no nodes or wires have |
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| 65 | been removed do not change the local implementation of LUTs |
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| 66 | even if alternate implementations are availabe from SPFD |
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| 67 | information. The default is to reprogram. |
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| 68 | |
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| 69 | -t <sec> |
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| 70 | Time in seconds allowed to complete the command. If the |
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| 71 | computation time goes above that limit, the process is is |
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| 72 | aborted. The default is no limit. |
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| 73 | |
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| 74 | -v <n> |
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| 75 | Verbosity level. |
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| 76 | |
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| 77 | -w <file> |
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| 78 | File to output final optimized circuit. |
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| 79 | |
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| 80 | The following is needed by VPR: |
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| 81 | |
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| 82 | net_file |
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| 83 | The description of the circuit in the .net format. Logic |
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| 84 | optimization uses the circuit described in .BLIF format whereas |
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| 85 | VPR needs the same circuit described in .net format. VPack |
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| 86 | (which comes with VPR) converts a .BLIF format into a .net |
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| 87 | format. |
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| 88 | |
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| 89 | arch_file |
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| 90 | Architecture description file for FPGAs. More information can |
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| 91 | be found in VPR's manual. |
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| 92 | |
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| 93 | place_file |
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| 94 | File to dump placement information. |
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| 95 | |
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| 96 | route_file |
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| 97 | File to dump routing information. |
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| 98 | |
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| 99 | Relevant flags to be set by the set command: |
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| 100 | |
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| 101 | spfd_pdlo_logic_move_freq "r1 m1 r2 m2 ..." |
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| 102 | Perform m1 logic moves whenever the rate of acceptance |
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| 103 | during simulated annealing is greater than or equal to |
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| 104 | r1, and so on. r1, r2, r3 ... should be monotonically |
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| 105 | decreasing, else the results would be unpredictable. 0 <= |
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| 106 | ri <= 1.0. For example: |
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| 107 | |
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| 108 | set spfd_pdlo_logic_move_freq "0.8 0 0.5 5 0.2 10" |
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| 109 | |
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| 110 | In the above logic schedule, zero logic moves per |
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| 111 | temperature will be performed when the rate of acceptance |
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| 112 | is above 0.8, 5 logic moves between 0.8 and 0.5, 10 moves |
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| 113 | between 0.5 and 0.2. As no value is specified for |
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| 114 | acceptance rate close to 0.0, by default, 1 logic move |
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| 115 | per temperature will be performed. In this example it |
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| 116 | will be 1 logic move between 0.2 and 0.0. The quotes |
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| 117 | around the schedule are necessary. |
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| 118 | |
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| 119 | spfd_repl_rem |
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| 120 | If no, the logic optimization performs only wire removal. |
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| 121 | If yes, both wire replacement and removal are performed. |
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| 122 | |
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| 123 | spfd_pdlo_timing |
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| 124 | If set, use timing driven method to remove or replace |
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| 125 | wires on the critical path. If not set, use bounding box |
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| 126 | of the wires as the cost function. |
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| 127 | |
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| 128 | spfd_pdlo_timing_nodeorwire |
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| 129 | Remove/replace all the wires belonging to the most |
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| 130 | critical net. If not set, attempt to remove/replace only |
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| 131 | the most critical wire. |
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| 132 | |
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| 133 | spfd_pdlo_out_crit_nets_first |
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| 134 | Output the circuit in VPR's .net format with the nets |
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| 135 | appearing in the increasing order of their slack. If not |
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| 136 | set, the initial net order specified in the original |
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| 137 | circuit's .net file is used. The file is specified with |
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| 138 | -n option. This variable is valid only if |
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| 139 | spfd_pdlo_timing is set. |
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| 140 | |
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| 141 | spfd_pdlo_remap_clb_array |
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| 142 | During logic optimization, due to the removal of nodes in |
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| 143 | the network, the current size of FPGA might be bigger |
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| 144 | than it is necessary. In such cases, if this variable is |
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| 145 | set, the size of the FPGA is reduced to fit the current |
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| 146 | logic network. |
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| 147 | |
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| 148 | Relevant flags that are options to VPR: |
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| 149 | |
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| 150 | For detailed information on the following options please refer |
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| 151 | to the manual that accompanies VPR source distribution. |
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| 152 | |
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| 153 | vpr_nodisp |
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| 154 | vpr_fix_pins |
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| 155 | vpr_nx |
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| 156 | vpr_ny |
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| 157 | vpr_fast |
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| 158 | vpr_init_t |
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| 159 | vpr_alpha_t |
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| 160 | vpr_exit_t |
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| 161 | vpr_inner_num |
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| 162 | vpr_seet |
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| 163 | vpr_place_cost_exp |
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| 164 | vpr_place_chan_width |
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| 165 | __________________________________________________________ |
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| 166 | |
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| 167 | Last updated on 20050519 10h16 |
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| 168 | |
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| 169 | References |
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| 170 | |
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| 171 | 1. http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html |
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