source: vis_dev/vis-2.1/share/vis/help/spfd_pdloCmd.txt @ 11

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2  spfd_pdlo - Perform SPFD-based simultaneous placement and logic optimization.
3     _________________________________________________________________
4
5   spfd_pdlo  [-D  <depth>] [-h] [-n <file>] [-r] [-t <sec>] [-v <n>] [-w
6   <file>] net_file arch_file place_file route_file
7
8   This   command   performs  SPFD-based  combined  logic  and  placement
9   optimization  of  combinational  circuits mapped to LUT-based FPGAs to
10   improve  circuit  area and speed. The flexibilities in the circuit are
11   represented  by  SPFDs. The following references explain in detail the
12   theory behind SPFDs.
13
14   S.  Yamashita,  H.  Sawada,  and  A.  Nagoya.  A new method to express
15   functional  permissibilities for LUT based FPGAs and its applications.
16   In  International  Conference on Computer Aided Design, pages 254-261,
17   1996.
18
19   Subarnarekha  Sinha  and  Robert K. Brayton. Implementation and use of
20   SPFDs  in optimizaing Boolean networks. In International Conference on
21   Computer Aided Design, 1998.
22
23   The  command  implements  a technique that tightly links the logic and
24   placement  optimization  steps.  The  algorithm  is based on simulated
25   annealing.  Two  types  of moves, directed towards global reduction in
26   the  cost  function (total wire length), are accepted by the simulated
27   annealing algorithm: (1) wire removal/replacement, and (2) swapping of
28   a  pair  of blocks in the FPGA. Feedback from placement is valuable in
29   making  an  informed choice of a target wire during logic optimization
30   moves.  The logic optimization steps performed are similar to those of
31   spfd_pilo,  except  that the placement information is now used instead
32   of  the  fanout count. More information on this technique can be found
33   in :
34
35   Balakrishna Kumthekar and Fabio Somenzi. Power and delay reduction via
36   simultaneous  logic  and  placement  optimization in FPGAs. In Design,
37   Automation and Test in Europe, 2000.
38
39   The  command  produces  a  placement  file  which  is  used by VPR for
40   routing.
41
42   This  command  can  be  used  only  if  VIS  is  linked  with VPR 4.22
43   (Versatile  Place  and  Route),  the FPGA place and route tool [1]VPR,
44   from  the  University  of  Toronto.  Please  follow  the  instructions
45   provided  in  the  release  notes  to  use  VPR with VIS. You can also
46   contact kumtheka@avanticorp.com if you need more help.
47
48   Before calling this command a network should be created for the design
49   (use  flatten_hierarchy)  and  MDD  ids  for every node in the network
50   should  be  created  (static_order -o all -n append). Dynamic variable
51   ordering (dvo -e sift) can be enabled to reduce BDD sizes.
52
53   Command options:
54
55   -D <depth>
56          A cluster is computed which includes nodes within the specified
57          'depth'. The default value is 1.
58
59   -n <file>
60          File to output the optimized circuit in VPR's .net format.
61
62   -r
63          Do  not  reprogram  LUTs  if  no  structural  changes have been
64          performed  with in the cluster, i.e., if no nodes or wires have
65          been  removed  do  not  change the local implementation of LUTs
66          even  if  alternate  implementations  are  availabe  from  SPFD
67          information. The default is to reprogram.
68
69   -t <sec>
70          Time  in  seconds  allowed  to  complete  the  command.  If the
71          computation  time  goes  above  that  limit,  the process is is
72          aborted. The default is no limit.
73
74   -v <n>
75          Verbosity level.
76
77   -w <file>
78          File to output final optimized circuit.
79
80   The following is needed by VPR:
81
82   net_file
83          The  description  of  the  circuit  in  the  .net format. Logic
84          optimization uses the circuit described in .BLIF format whereas
85          VPR  needs  the  same  circuit  described in .net format. VPack
86          (which  comes  with  VPR)  converts  a .BLIF format into a .net
87          format.
88
89   arch_file
90          Architecture  description  file for FPGAs. More information can
91          be found in VPR's manual.
92
93   place_file
94          File to dump placement information.
95
96   route_file
97          File to dump routing information.
98
99          Relevant flags to be set by the set command:
100
101        spfd_pdlo_logic_move_freq "r1 m1 r2 m2 ..."
102                Perform  m1  logic  moves whenever the rate of acceptance
103                during  simulated  annealing  is greater than or equal to
104                r1,  and  so  on.  r1, r2, r3 ... should be monotonically
105                decreasing, else the results would be unpredictable. 0 <=
106                ri <= 1.0. For example:
107
108                set spfd_pdlo_logic_move_freq "0.8 0 0.5 5 0.2 10"
109
110                In  the  above  logic  schedule,  zero  logic  moves  per
111                temperature will be performed when the rate of acceptance
112                is above 0.8, 5 logic moves between 0.8 and 0.5, 10 moves
113                between  0.5  and  0.2.  As  no  value  is  specified for
114                acceptance  rate  close  to 0.0, by default, 1 logic move
115                per  temperature  will  be  performed. In this example it
116                will  be  1  logic  move  between 0.2 and 0.0. The quotes
117                around the schedule are necessary.
118
119        spfd_repl_rem
120                If no, the logic optimization performs only wire removal.
121                If yes, both wire replacement and removal are performed.
122
123        spfd_pdlo_timing
124                If  set,  use  timing  driven method to remove or replace
125                wires  on the critical path. If not set, use bounding box
126                of the wires as the cost function.
127
128        spfd_pdlo_timing_nodeorwire
129                Remove/replace  all  the  wires  belonging  to  the  most
130                critical  net. If not set, attempt to remove/replace only
131                the most critical wire.
132
133        spfd_pdlo_out_crit_nets_first
134                Output  the  circuit  in  VPR's .net format with the nets
135                appearing  in the increasing order of their slack. If not
136                set,  the  initial  net  order  specified in the original
137                circuit's  .net  file is used. The file is specified with
138                -n    option.    This   variable   is   valid   only   if
139                spfd_pdlo_timing is set.
140
141        spfd_pdlo_remap_clb_array
142                During logic optimization, due to the removal of nodes in
143                the  network,  the  current  size of FPGA might be bigger
144                than  it is necessary. In such cases, if this variable is
145                set,  the  size of the FPGA is reduced to fit the current
146                logic network.
147
148          Relevant flags that are options to VPR:
149
150          For  detailed information on the following options please refer
151          to the manual that accompanies VPR source distribution.
152
153        vpr_nodisp
154        vpr_fix_pins
155        vpr_nx
156        vpr_ny
157        vpr_fast
158        vpr_init_t
159        vpr_alpha_t
160        vpr_exit_t
161        vpr_inner_num
162        vpr_seet
163        vpr_place_cost_exp
164        vpr_place_chan_width
165            __________________________________________________________
166
167          Last updated on 20050519 10h16
168
169References
170
171   1. http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html
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